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參數(shù)資料
| 型號(hào)： | T7237A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 63/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7237A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
59
Application Briefs
(continued)
Using the T7256 in a Combination TE/TA
Environment (NT1/TA)
The T7256 can be used in applications requiring NT1
and terminal adapter (TA) functionality (NT1/TA). This
application brief describes an NT1 that supports con-
ventional POTS (plain old telephone service) as well as
ISDN service. A block diagram of this application is
shown in Figure 22. The microprocessor (
μ
P) performs
the following functions:
I
Runs the ISDN call control stack (Q.931).
I
Controls the HDLC formatter for performing the
LAP-D protocol on the D channel.
I
Controls the register configuration of the T7256.
I
Controls the POTS circuitry (i.e., translates signaling
such as off-hook into the correct call-control mes-
sage, translates DTMF digits from a DTMF receiver,
controls the ringer, etc.).
I
Controls access to the B and D channels on the TDM
highway for the codecs and HDLC formatter, respec-
tively.
5-3646(C).b
Figure 22. T7256 NT1/TA Application Block Diagram
T7256 Configuration
When the T7256 is used in the NT1/TA application, the
TDM highway must be used in conjunction with the
data flow control registers (DFR0 and DFR1) to control
the B- and D-channel data flow. Following is a sug-
gested procedure for properly configuring the T7256 in
this application.
1. Set TDMEN = 0 (register GR2, bit 5) to enable the
TDM highway. In this case, the ps1/ps2 functions
must be controlled via the microprocessor (register
GR1, bits 1 and 2) because pins 8 and 9 are used
for TDMDO and TDMCLK. Note that when the TDM
highway is enabled, TDMCLK and FS will not
become active until at least one of the bits 2—7 in
register DFR1 are enabled (set to 0).
2. The downstream D channel must be monitored by
the TA circuit for call-control messages from the
switch. This is accomplished via the TDM bus by
setting TDMDU = 0 (register DFR1, bit 7). The
upstream D channel (which is normally sourced
from the S/T-interface) must be sourced by the
POTS HDLC controller when one of the following
events occurs:
a. The switch notifies the POTS circuit of an incom-
ing call request via a downstream D-channel
message.
b. A local POTS phone goes off-hook (i.e., a call is
being placed).
In either of these cases, the POTS HDLC controller
must take control of the D-channel in order to com-
plete the call setup for the appropriate POTS phone.
This is accomplished by setting UXD = 0 (register
DFR1, bit 0).
3. The frame strobe pulse envelope and polarity must
be configured for correct operation with the HDLC
controller and codecs using register TDR0. For
example, to set an active-high FS pulse that enve-
lopes the U-interface B1 channel data (see Figure
18), register TDR0 bits 0—3 should be set to all 1s
(default on powerup). This setting can be used with
the Lucent T7121 HDLC controller because the
T7121 can be programmed for any time slot and bit
offset from the rising or falling edge of FS.
The codecs may require the FS pulse be in a partic-
ular position relative to the B-channel data. For
example, if two Lucent T7513B codecs are used in
variable timing mode in this application (one for
each POTS line), each would require an FS pulse
that envelopes the appropriate B-channel data. The
configuration described in the preceding paragraph
is adequate for allowing either codec to source or
sink B1 channel data to the U-interface, but there is
no separate FS pulse available for the B2 channel
data. Therefore, external glue logic is necessary to
generate an FS pulse for the B2 channel data.
T7256
U-INTERFACE
SERIAL INTERFACE
μP
PARALLEL INTERFACE
HDLC
CODEC,
SLICS, RINGERS, DTMF
RECEIVERS, ETC.
TDM HIGHWAYS
S/T-INTERFACE
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