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參數(shù)資料
| 型號(hào)： | T7237A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 16/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7237A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
12
Lucent Technologies Inc.
Functional Overview
(continued)
When the T7256 is powered on and there is no activity
on the S/T- or U-interfaces (i.e., no pending activation
request), it automatically enters a low-power IDLE
mode in which it consumes an average of 35 mW.
This mode is exited automatically when an activation or
U maintenance request occurs from either the micro-
processor or the S/T- or U-interfaces. The T7256 pro-
vides a board-level test capability that allows functional
verification. Finally, an LED driver output indicates the
status of the device during operation.
U-Interface Frame Structure
Data is transmitted over the U-interface in 240-bit
groups called U frames. Each U frame consists of an
18-bit synchronization word or inverted synchronization
word (SW or ISW), 12 blocks of 2B+D data (216 bits),
and six overhead bits (M bits). A U-interface super-
frame consists of eight U frames grouped together. The
beginning of a U superframe is indicated by the
inverted sync word (ISW). The six overhead bits (M1—
M6) from each of the eight U frames, when taken
together, form the 48 M bits. Figure 4 shows how U
frames, superframes, and M bits are arranged.
Of the 48 M bits, 24 bits form the embedded operations
channel (eoc) for sending messages from the LT to the
NT and responses from the NT to the LT. There are two
eoc messages per superframe with 12 bits per eoc
message (eoc1 and eoc2). Another 12 bits serve as U-
interface control and status bits (UCS). The last 12 bits
form the cyclic redundancy check (CRC) which is cal-
culated over the 2B+D data and the M4 bits of the pre-
vious superframe. Figure 5 and Table 2 show the
different groups of bits in the superframe.
5-2476 (C)
Figure 4. U-Interface Frame and Superframe
U1
U2
U3
U4
U5
U6
U7
U8
U-INTERFACE M BITS [48]
U-FRAME SPAN = 1.5 ms
U-SUPERFRAME SPAN = 12 ms
ISW[18]
(2B+D) x 12 [ 216 bits]
M[6]
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