
IX-10
Index
selection response logic test (SLT)
4-92
semaphore (SEM)
4-52
serial EEPROM
data format
2-58
interface
2-57
SERR/
3-9
SERR/ enable (SE)
4-3
set instruction
5-16
,
5-18
set/clear
carry
5-21
SACK/
5-21
SATN/
5-22
target mode
5-21
shadow register test mode (SRTM)
4-63
SIDL
least significant byte full (ILF)
4-45
most significant byte full (ILF1)
4-49
signal names
and BGA position
6-64
by BGA position
6-64
signal process (SIGP)
4-52
,
4-58
signaled system error (SSE)
4-5
simple arbitration
4-22
single
address cycles
2-20
ended SCSI signals
6-7
step interrupt (SSI)
4-43
,
4-71
step mode (SSM)
4-73
SIP
2-43
,
2-46
slow memory ( 128 Kbytes)
read cycle
6-52
write cycle
6-54
slow ROM pin
3-24
SLPAR high byte enable (SLPHBEN)
4-29
SLPAR mode (SLPMD)
4-29
SODL
least significant byte full (OLF)
4-45
most significant byte full (OLF1)
4-50
register
2-52
SODR
least significant byte full (ORF)
4-45
most significant byte full (ORF1)
4-49
software reset (SRST)
4-52
source
I/O-memory enable (SIOM)
4-69
special cycle command
2-5
SREQ
2-47
stacked interrupts
2-46
start
address
5-14
,
5-22
DMA operation (STD)
4-74
SCSI transfer (SST)
4-27
sequence (START)
4-23
static block move selector (SBMS)
4-108
status register
4-5
STOP command
2-9
stop signal
3-8
STOP/
3-8
store instruction
2-23
stress ratings
6-1
subsystem ID
2-58
(SID)
4-12
subsystem vendor ID
2-58
(SVID)
4-11
SWIDE register
2-52
SYM53C700 compatibility (COM)
4-74
SYM53C896
329 ball grid array
6-66
329 BGA mechanical drawing
6-67
new features
1-3
register map
A-1
SYNC_IRQD (SI)
4-55
synchronous
clock conversion factor (SCF[2:0])
4-31
data transfer rates
2-39
operation
2-39
SCSI receive
2-31
SCSI send
2-30
system error
3-9
system signals
3-5
T
table indirect
5-6
,
5-20
mode
5-19
table relative
5-20
target
asynchronous receive
6-59
asynchronous send
6-59
mode
5-10
,
5-15
SATN/ active (M/A)
4-79
mode (TRG)
4-24
ready
3-7
synchronous transfer
6-63
timing
6-15
TCK
3-20
TDI
3-20
TDO
3-20
TEMP register
5-37
temporary (TEMP)
4-61
termination
2-37
test clock
3-20
test data in
3-20
test data out
3-20
test halt SCSI clock
3-20
test interface signals
3-20
test mode select
3-20
test reset
3-20
TEST_HSC
3-20
TEST_RSTN
3-20
third dword
5-14
,
5-33
,
5-36
timer test mode (TTM)
4-98
TMS
3-20
TolerANT
1-5
enable (TE)
4-96
technology
1-5
benefits
1-5
electrical characteristics
6-7
Totem Pole Output
3-3
transfer
control
2-23
control instructions
5-27
and SCRIPTS instruction prefetching
2-23
count
5-35
counter
5-13
information
2-18
rate synchronous
2-39
TRDY/
2-9
,
3-7
U
ultra SCSI