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參數(shù)資料
| 型號： | ST62T45B |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 52/72頁 |
| 文件大?。?/td> | 514K |
| 代理商： | ST62T45B |
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ST62T45B/E45B
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and In-
put/Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Immediate
. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As theoperand is a ROM byte,the imme-
diate addressing mode is used to access con-
stants which do not change during program exe-
cution (e.g., a constant used to initialize a loop
counter).
Direct
. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode.
Direct addressing allows the user to directly ad-
dress the 256 bytes in Data Space memory with a
single two-byte instruction.
Short Direct
. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h)
in the short-direct addressing mode. In this case,
the instruction is only one byte and the selection of
the location to be processed is contained in the
opcode. Short direct addressing is a subset of the
direct addressing mode. (Note that 80h and 81h
are also indirect registers).
Extended
. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative
. The relative ad-
dressing mode is only used in conditional branch
instructions. The instruction is used to perform a
test and, if the condition is true, a branch with a
span of -15 to +16 locations around the address of
the relative instruction. If the condition is not true,
the instruction which follows the relative instruc-
tion is executed. The relative addressing mode in-
struction is one-byte long. The opcode is obtained
in adding the three most significant bits which
characterize the kind of the test, one bit which de-
termines whether the branch is a forward (when it
is 0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to the address of the relative instruction to
obtain the address of the branch.
Bit Direct
. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Bit Test & Branch
. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Indirect
. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the
indirect registers, X or Y (80h,81h). The indirect
register is selected by the bit 4 of the opcode. A
register indirect instruction is one byte long.
Inherent
. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
51
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST62T45BQ6 | 功能描述:8位微控制器 -MCU OTP EPROM 8K RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST62T45Q6 | 制造商:STMicroelectronics 功能描述:8BIT MCU - Bulk |
| ST62T46BB6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST62T52CB6 | 功能描述:8位微控制器 -MCU OTP EPROM 2K No Intf RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST62T52CM3 | 制造商:STMicroelectronics 功能描述: 制造商:STMicroelectronics 功能描述:MCU 8BIT ST6 CISC 1836BYTE EPROM 5V 16SOIC - Rail/Tube |
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