參數(shù)資料
型號(hào)： ST62T45B
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù)： 24/72頁(yè)
文件大?。?/td> 514K
代理商： ST62T45B
24/72
ST62T45B/E45B
DIGITAL WATCHDOG
(Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR)
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to
the user’s requirements by setting the appropriate
value for bits T0 to T5 in the DWDR register. The
SR bit must be set to “1”, since it is this bit which
generates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set.
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated inFigure 14.
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer pe-
riods ranging from 384
μ
s to 24.576ms).
Figure 14.Watchdog Counter Control
W
D0
D1
D3
D4
D5
D6
D7
W
C
SR
T5
T4
T3
T2
T1
D2
T0
OSC
÷
12
RESET
VR02068A
÷
2
8
23
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