參數(shù)資料
型號(hào)： ST62T45B
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù)： 47/72頁(yè)
文件大?。?/td> 514K
代理商： ST62T45B
47/72
ST62T45B/E45B
SERIAL PERIPHERAL INTERFACE
(Cont’d)
After 8 clock pulses (D7..D0) the output Q4 of the
4-bit binary counter becomes low, disabling the
clock from the counter and the data/shift register.
Q4 enables the clock to generate an interrupt on
the 8th clock falling edge as long as no reset of the
counter (processor write into the 8-bit data/shift
register) takes place. After a processor reset the
interrupt is disabled. The interrupt is active when
writing data in the shift register and desactivated
when writing any data in the SPI Interrupt Disable
register.
The generation of an interrupt to the Core pro-
vides information that new data is available (input
mode) or that transmission is completed (output
mode), allowing the Core to generate an acknowl-
edge on the 9th clock pulse (I
C-b
us).
The interrupt is initiated by a high to low transition,
and therefore interrupt options must be set ac-
cordingly as defined in the interrupt section.
After power on reset, or after writing the data/shift
register, the counter is reset to zero and the clock
is enabled. In this condition the data shift register
is ready for reception. No start condition has to be
detected. Through the user software the Core may
pull down the Sin line (Acknowledge) and slow
down the SCL, as long as it is needed to carry out
data from the shift register.
I C-bus Master-Slave, Receiver-Transmitter
When pins Sin and Sout are externally connected
together it is possible to use the SPI as a receiver
as well as a transmitter. Through software routine
(by using bit-set and bit-reset on I/O line) a clock
can be generated allowing
I C-bu
s to work inmas-
ter mode.
When implementing an
I C-b
us protocol, the start
condition can be detected by setting the processor
into a wait for start condition by enabling the inter-
rupt of the I/O port used for the Sin line. This frees
the processor from polling the Sin and SCL lines.
After the transmission/reception the processor
has to poll for the STOP condition.
In slave mode the user software can slow down
the SCL clock frequency by simply putting the
SCL I/O line in output open-drain mode and writ-
ing a zero into the corresponding data register bit.
As it is possible to directly read the Sin pin directly
through the port register, the software can detect a
difference between internal data and external data
(master mode). Similar condition can be applied to
the clock.
Three (Four) Wire Serial Bus
It is possible to use a single general purpose I/O
pin (with the corresponding interrupt enabled) as a
chip enable pin. SCL acts as active or passive
clock pin, Sin as data in and Sout as data out (four
wire bus). Sin and Sout can be connected togeth-
er externally to implement three wire bus.
Note
:
When the SPI is not used, the three I/O lines (Sin,
SCL, Sout) can be used as normal I/O, with the
following limitation: bit Sout cannot be used in
open drain mode as this enables the shift register
output to the port.
It is recommended, in order to avoid spurious in-
terrupts from the SPI, to disable the SPI interrupt
(the default state after reset) i.e. no write must be
made to the 8-bit shift register. An explicit interrupt
disable may be made in software by a dummy
write to the SPI interrupt disable register.
SPI Data/Shift Register
Address: DDh - Read/Write (SDSR)
A write into this register enables SPI Interrupt after
8 clock pulses.
SPI Interrupt Disable Register
Address: C2h - Read/Write (SIDR)
A dummy write to this register disables SPI Inter-
rupt.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
46
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