參數(shù)資料
型號(hào)： ST62T45B
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù)： 21/72頁(yè)
文件大?。?/td> 514K
代理商： ST62T45B
21/72
ST62T45B/E45B
RESETS
(Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 Application Notes
No external resistor is required between V
and
the Reset pin, thanks to the built-in pull-up device.
The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
edge of V
. The typical threshold is in the region
of 2 volts, but the actual value of the detected
threshold depends on the way in which V
DD
rises.
The POR circuit is NOT designed to supervise
static, or slowly rising or falling V
DD
.
3.2.5 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (lo-
cated in program ROM starting at address
0FFEh). A jump to the beginning of the user pro-
gram must be coded at this address. Following a
Reset, the Interrupt flag is automatically set, so
that the CPU is in Non Maskable Interrupt mode;
this prevents the initialisation routine from being
interrupted. The initialisation routine should there-
fore be terminated by a RETI instruction, in order
to revert to normal mode and enable interrupts. If
no pending interrupt is present at the end of the in-
itialisation routine, the MCU will continue by
processing the instruction immediately following
the RETI instruction. If, however, a pending inter-
rupt is present, it will be serviced.
Figure 12. Reset and Interrupt Processing
Figure 13. Reset Block Diagram
RESET
RESET
VECTOR
JP
JP:2 BYTES/4 CYCLES
RETI
RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
V
DD
RESET
300k
2.8k
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
f
OSC
RESET
ON RESET
VA0200B
20
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