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| 型號： | ST62T45B |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 27/72頁 |
| 文件大?。?/td> | 514K |
| 代理商： | ST62T45B |
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ST62T45B/E45B
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source is as-
sociated with a specific Interrupt Vector which
contains a Jump instruction to the associated in-
terrupt service routine. These vectors are located
in Program space (seeTable 8).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt sources are linked to events either on ex-
ternal pins, or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are processed by the processor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Table 8. Interrupt Vector Map
3.4.1 Interrupt request
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GENbit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can
restart the MCU from STOP/WAIT modes.
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is auto-
matically reset by the core at the beginning of the
non-maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting
accordingly the LES bit of the Interrupt Option
Register (IOR).
Interrupt request from source #2 are always edge
sensitive. The edge polarity can be configured by
setting accordingly the ESB bit of the Interrupt Op-
tion Register (IOR).
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Storage of interrupt requests is not available in
level sensitive mode. To be taken into account,
the low level must be present on the interrupt pin
when the MCU samples the line after instruction
execution.
At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Table 9.Interrupt Option Register Description
Interrupt Source
Interrupt source #0
Interrupt source #1
Interrupt source #2
Interrupt source #3
Interrupt source #4
Priority
1
2
3
4
5
Vector Address
(FFCh-FFDh)
(FF6h-FF7h)
(FF4h-FF5h)
(FF2h-FF3h)
(FF0h-FF1h)
GEN
SET
CLEARED
Enable all interrupts
Disable all interrupts
Rising edge mode on inter-
rupt source #2
Falling edge mode on inter-
rupt source #2
Level-sensitive mode on in-
terrupt source #1
Falling edge mode on inter-
rupt source #1
ESB
SET
CLEARED
LES
SET
CLEARED
OTHERS
NOT USED
26
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