
ST20-GP1
98/116
DC specifications
Notes
1
2
This is the static specification to ensure low current.
Output current of 2mA.
3
4
Output current of -2mA.
Excludes power used to drive external loads. Includes operation of the 32 KHz watch crys-
tal oscillator.
5
Device operation suspended by use of the low power controller with
VDD
and
RTCVDD
within specification. Frequency of system clock (fclk) is 16.368 MHz and frequency of low
power clock is 32768 Hz.
6
With
RTCVDD
within specification and
VDD
at 0 V. All inputs static except
LowPower-
ClockIn
and
LowPowerClockOsc
, frequency of low power clock 32768 Hz. All other
inputs must be in the range -0.1 to 0.1 V.
Symbol
Parameter
Min
Typical Max
Units
Notes
V
DD
Positive supply voltage during normal operation.
3.0
3.3
3.6
V
V
DDoff
Positive supply voltage when device is off but real time
clock is running.
-0.3
0
0.3
V
V
DDrtc
Voltage at
RTCVDD
pin referred to
GND
.
3.0
3.3
3.6
V
V
DDdiff
V
DD
-V
DDrtc
during normal operation and
notRST
set to
1.
-0.3
0
0.3
V
1
V
ih
Input logic 1 for
LPClockIn
,
notRST
and test control pins.
Input logic 1 for all other inputs.
PIO pins.
2.0
2.0
2.4
V
DDrtc
+ 0.5
V
DD
+ 0.5
V
DD
+ 0.5
V
V
il
Input logic 0 for all inputs.
-0.5
0.8
I
in
Input current to input pins.
-10
10
μ
A
μ
A
V
I
oz
Off state digital output current.
-50
50
V
ohdc
Output logic 1
2.4
V
DD
2
V
oldc
Output logic 0
0
0.4
3
C
in
Input capacitance (input only pins).
4
10
pF
C
out
Output capacitance and capacitance of bidirectional pins.
6
15
pF
P
op
Operational power consumption under heavy device
activity. fclk of 16.368 MHz and
SpeedSelect
set to PLL
operation (x1). No external memory used.
0.5
0.8
W
4
P
app
Operational power consumption under ‘typical’ device
activity. fclk of 16.368 MHz and
SpeedSelect
set to PLL
operation (x2). External memory used.
0.75
1.1
W
4
P
stby
Operational power during stand-by.
0.16
0.3
W
5
P
rtc
Operational power for the real time clock only, supplied
through the
RTCVDD
pin.
1
mW
6
Table 17.3 DC specification