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參數(shù)資料
| 型號： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁數(shù)： | 75/116頁 |
| 文件大小： | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
75/116
Figure 13.3 9-bit data frames
Transmission
Transmission begins at the next overflow of the divide-by-16 counter (see Figure 13.3 above),
provided that the
Run
bit is set and data has been loaded into the
ASCTxBuffer
. The transmitted
data frame consists of three basic elements:
the start bit
the data field (8 or 9 bits, least significant bit (LSB) first, including a parity bit, if selected)
the stop bits (0.5, 1, 1.5 or 2 stop bits)
Data transmission is double buffered. When the transmitter is idle, the transmit data written into the
transmit buffer is immediately moved to the transmit shift register, thus freeing the transmit buffer
for the next data to be sent. This is indicated by the transmit buffer empty flag (
TxBufEmpty
) being
set. The transmit buffer can be loaded with the next data, while transmission of the previous data is
still going on.
The transmitter empty flag (
TxEmpty
) will be set at the beginning of the last data frame bit that is
transmitted, i.e. during the first system clock cycle of the first stop bit shifted out of the transmit shift
register.
Reception
Reception is initiated by a falling edge on the data input pin (
RXD
), provided that the
Run
and
RxEnable
bits are set. The
RXD
pin is sampled at 16 times the rate of the selected baud rate. A
majority decision of the first, second and third samples of the start bit determines the effective bit
value. This avoids erroneous results that may be caused by noise.
If the detected value is not a 0 when the start bit is sampled, the receive circuit is reset and waits
for the next falling edge transition of the
RXD
pin. If the start bit is valid, the receive circuit
continues sampling and shifts the incoming data frame into the receive shift register. For
subsequent data and parity bits, the majority decision of the seventh, eighth and ninth samples in
each bit time is used to determine the effective bit value.
For 0.5 stop bits, the majority decision of the third, fourth, and fifth samples during the stop bit is
used to determine the effective stop bit value.
For 1 and 2 stop bits, the majority decision of the seventh, eighth, and ninth samples during the
stop bits is used to determine the effective stop bit values.
1st
stop
bit
2nd
stop
bit
start
bit
D0
(LSB)
D1
D2
D3
D4
D5
D6
9th
bit
D7
Data bit (
D8
)
Parity bit
Wake-up bit
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PDF描述 |
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| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
| ST25C02AM6 | Cyclone II FPGA 20K FBGA-256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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