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參數(shù)資料
| 型號： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁數(shù)： | 34/116頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
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6
Instruction set
This chapter provides information on the instruction set. It contains tables listing all the instructions,
and where applicable provides details of the number of processor cycles taken by an instruction.
The instruction set has been designed for simple and efficient compilation of high-level languages.
All instructions have the same format, designed to give a compact representation of the operations
occurring most frequently in programs.
Each instruction consists of a single byte divided into two 4-bit parts. The four most significant bits
(MSB) of the byte are a function code and the four least significant bits (LSB) are a data value, as
shown in Figure 6.1.
Figure 6.1 Instruction format
For further information on the instruction set refer to the ST20 Instruction Set Manual (document
number 72-TRN-273-01).
6.1
Instruction cycles
Timing information is available for some instructions. However, it should be noted that many
instructions have ranges of timings which are data dependent.
Where included, timing information is based on the number of clock cycles assuming any memory
accesses are to 2 cycle internal memory and no other subsystem is using memory. Actual time will
be dependent on the speed of external memory and memory bus availability.
Note that the actual time can be increased by:
1
the instruction requiring a value on the register stack from the final memory read in the pre-
vious instruction — the current instruction will stall until the value becomes available.
2
the first memory operation in the current instruction can be delayed while a preceding mem-
ory operation completes — any two memory operations can be in progress at any time, any
further operation will stall until the first completes.
3
memory operations in current instructions can be delayed by access by instruction fetch or
subsystems to the memory interface.
4
there can be a delay between instructions while the instruction fetch unit fetches and par-
tially decodes the next instruction — this will be the case whenever an instruction causes
the instruction flow to jump.
Note that the instruction timings given refer to ‘standard’ behavior and may be different if, for
example, traps are set by the instruction.
Function
Data
7
4 3
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
| ST25C02AM6 | Cyclone II FPGA 20K FBGA-256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR |
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