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參數(shù)資料
| 型號(hào)： | ST20GP1 |
| 英文描述： | MAX 7000 CPLD 256 MC 208-PQFP |
| 中文描述： | GPS處理器 |
| 文件頁(yè)數(shù)： | 56/116頁(yè) |
| 文件大?。?/td> | 1107K |
| 代理商： | ST20GP1 |
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ST20-GP1
56/116
in the following two cases:
The previous access was a read and the pending one is a write. The write access will not
start until the programmed number of
BusReleaseTime
cycles have elapsed.
The previous access was to a different bank to the pending access (bank switch). One
cycle is always inserted between accesses to different banks. Note that, if the first condition
is also true, further cycles may be inserted to account for
BusReleaseTime
.
The first case may be optimized slightly by making use of the
DataDriveDelay
configuration
register parameter, see Table 9.4. When this is used, the programmed
BusReleaseTime
may be
smaller, reducing the number of dead cycles, see Figure 9.4.
Figure 9.4 Use of DataDriveDelay parameter
Note, if
DataDriveDelay
is used, it must be used for all banks. If this rule is not adhered to, bus
contention may occur on bank switches. For example, consider case 2 in Figure 9.4 above. If the
BusReleaseTime
coincides with the dead cycle inserted due to a bank switch, contention will
occur unless
DataDriveDelay
is programmed in the same way as if no bank switch had occurred.
9.4
MemWait
When enabled (see Table 9.4),
MemWait
is sampled at the midpoint of accesses which are
configured to be four cycles or greater. If the duration of the external access is not an even number
of cycles (i.e. the
AccessDuration
bit field in the
EMIConfigData
register, see Table 9.4, is an odd
number),
MemWait
is sampled on the internal rising clock edge just after the midpoint of the
access.
Once a high has been sampled, the access is stalled.
MemWait
suspends the state of the EMI in
the cycle after it is sampled high. The state remains suspended until
MemWait
is sampled low. Any
strobe edges scheduled to occur in the cycle after
MemWait
is sampled will not occur. Strobe
edges scheduled to occur on the same edge as
MemWait
is sampled are not affected. Figure 9.5
and Figure 9.6 show the extension of the external memory cycle and the delaying of strobe
Read
Write
BusRelease
time
Case 1.
DataDriveDelay
set
to zero. All dead time taken up
by
BusReleaseTime
.
Read
Write
BusRelease
time
DataDriveDelay
Case 2.
DataDriveDelay
used
to absorb some
BusReleaseTime
. Dead time
may be reduced.
Read data
Read data
Write data
Write data
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| ST20GP6 | MAX 7000 CPLD 256 MC 208-RQFP |
| ST25C02AB1 | IC FLEX 6000 FPGA 16K 144-TQFP |
| ST25C02AB6 | Stratix FPGA 25K FBGA-672 |
| ST25C02AM1 | IC ACEX 1K FPGA 100K 208-PQFP |
| ST25C02AM6 | Cyclone II FPGA 20K FBGA-256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST20-GP1 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP1X33S | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:GPS PROCESSOR |
| ST20-GP6 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:GPS PROCESSOR |
| ST20GP6CT33S | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:GPS PROCESSOR |
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