參數(shù)資料
型號： ST16C554DIQ64TR-F
廠商： Exar Corporation
文件頁數(shù)： 39/39頁
文件大?。?/td> 0K
描述： IC UART FIFO 16B QUAD 64LQFP
標準包裝： 1,000
特點： *
通道數(shù)： 4，QUART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
ST16C554/554D
9
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
2.4
Channels A-D Internal Registers
Each UART channel in the 554 has a set of enhanced registers for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR). All the register functions are discussed in full detail later in “Section
2.5
INT Ouputs for Channels A-D
The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4
summarize the operating behavior for the transmitter and receiver. Also see Figure 17 through 22.
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide
additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the
transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit
and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the
DMA mode is disabled (FCR bit-3 = 0), the 554 is placed in single-character mode for data transmit or receive
operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by
TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
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