參數(shù)資料
型號: ST16C554DIQ64TR-F
廠商: Exar Corporation
文件頁數(shù): 1/39頁
文件大小: 0K
描述: IC UART FIFO 16B QUAD 64LQFP
標(biāo)準(zhǔn)包裝: 1,000
特點: *
通道數(shù): 4,QUART
FIFO's: 16 字節(jié)
規(guī)程: RS232
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
JUNE 2006
REV. 4.0.1
GENERAL DESCRIPTION
The ST16C554/554D (554) is a quad Universal
Asynchronous Receiver and Transmitter (UART) with
16 bytes of transmit and receive FIFOs, selectable
receive FIFO trigger levels and data rates of up to 1.5
Mbps. Each UART has a set of registers that provide
the user with operating status and control, receiver
error
indications,
and
modem
serial
interface
controls.
An internal loopback capability allows
onboard diagnostics. The 554 is available in a 64-pin
LQFP and a 68-pin PLCC package.
The 64-pin
package only offers the 16 mode interface, but the
68-pin
package
offers
an
additional
68
mode
interface which allows easy integration with Motorola
processors.
The ST16C554CQ64 (64-pin) offers
three
state
interrupt
output
while
the
ST16C554DCQ64
provides
continuous
interrupt
output. The 554 combines the package interface
modes of the 16C554 and 68C554 on a single
integrated chip.
FEATURES
Pin-to-pin compatible with the industry standard
ST16C454,
ST68C454,
ST68C554,
TI’s
TL16C554A and Philips’ SC16C554B
Intel or Motorola Data Bus Interface select
Four independent UART channels
Register Set Compatible to 16C550
Data rates of up to 1.5 Mbps at 5 V
Data rates of up to 500 Kbps at 3.3V
16 byte Transmit FIFO
16 byte Receive FIFO with error tags
4 Selectable RX FIFO Trigger Levels
Full modem interface
2.97V to 5.5V supply operation
Crystal oscillator or external clock input
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FIGURE 1. ST16C554 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc / Buffer
Data Bus
Interface
UART Channel A
16 Byte TX FIFO
16 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.97 V to 5.5 V VCC
GND
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
16/68#
CSB#
INTA
INTB
IOW#
IOR#
Reset
INTSEL
TXRDY#A-D
RXRDY#A-D
UART Channel C
(same as Channel A)
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
UART Channel D
(same as Channel A)
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
CSC#
CSD#
INTC
INTD
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