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ST16C554/554D
25
REV. 4.0.1
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
TABLE 13: UART RESET CONDITIONS FOR CHANNELS A-D
REGISTERS
RESET STATE
DLM, DLL
DLM and DLL are unknown upon power up. They do
not reset when the Reset Pin is asserted.
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
I/O SIGNALS
RESET STATE
TX
HIGH
IRTX
LOW
RTS#
HIGH
DTR#
HIGH
RXRDY#
HIGH
TXRDY#
LOW
INT
(16 Mode)
ST16C554 = Three-State Condition (INTSEL = LOW)
ST16C554 = LOW (INTSEL = HIGH)
ST16C554D = LOW
IRQ#
(68 Mode)
HIGH (INTSEL = LOW)