參數(shù)資料
型號： SSTUB32868ET/S
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176
封裝： 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件頁數(shù)： 9/30頁
文件大?。?/td> 254K
代理商： SSTUB32868ET/S
SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
17 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
10. Characteristics
[1]
Instantaneous is defined as within < 2 ns following the output data transition edge.
Table 8.
Characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage IOH = 6mA; VDD = 1.7 V
1.2
-
V
VOL
LOW-level output voltage
IOL =6mA; VDD =1.7 V
-
0.5
V
II
input current
all inputs; VI =VDD or GND; VDD =1.9 V
-
±5
μA
IDD
supply current
static standby; RESET = GND; VDD =1.9 V;
IO =0mA
--
2
mA
static operating; RESET =VDD;
VDD =1.9 V; IO =0mA;
VI =VIH(AC) or VIL(AC)
--
80
mA
IDDD
dynamic operating current
per MHz
clock only; RESET =VDD;
VI =VIH(AC) or VIL(AC); CK and CK switching
at 50 % duty cycle. IO =0 mA; VDD =1.8 V
-16
-
μA
per each data input (1 : 1 mode);
RESET =VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle;
one data input switching at half clock
frequency, 50 % duty cycle; IO =0mA;
VDD =1.8 V
-19
-
μA
per each data input (1 : 2 mode);
RESET =VDD; VI =VIH(AC) or VIL(AC);
CK and CK switching at 50 % duty cycle;
one data input switching at half clock
frequency, 50 % duty cycle; IO =0mA;
VDD =1.8 V
-19
-
μA
Ci
input capacitance
Dn, CSGEN, PAR_IN inputs;
VI =Vref ± 250 mV; VDD =1.8 V
2.5
-
4
pF
DCSn; VICR =0.9 V; VID = 600 mV;
VDD =1.8 V
2.5
-
4
pF
CK and CK; VICR =0.9 V; VID =600 mV;
VDD =1.8 V
2-
3
pF
RESET; VI =VDD or GND; VDD =1.8 V
3
-
5
pF
Zo
output impedance
normal drive; instantaneous
[1] -15
-
Ω
normal drive; steady-state
-
53
-
Ω
high drive; instantaneous
-
Ω
high drive; steady-state
-
53
-
Ω
Input RESET
VIL
LOW-level input voltage
0.5
-
+0.3VDD V
VIH
HIGH-level input voltage
0.7VDD -2.5
V
II
input current
VI =VDD
5-
+5
μA
IL
leakage current
VI =VSS
100
25
10
μA
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