參數(shù)資料
型號: SSTUB32868ET/S
廠商: NXP SEMICONDUCTORS
元件分類: 鎖存器
英文描述: 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176
封裝: 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件頁數(shù): 6/30頁
文件大?。?/td> 254K
代理商: SSTUB32868ET/S
SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
14 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
(1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be generated on
the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. If an error occurs and the QERR output is driven LOW, it
stays LOW for a minimum of two clock cycles or until RESET is driven LOW.
Fig 7.
Timing diagram during normal operation (RESET = HIGH)
CK
Dn, DODTn,
DCKEn
Qn, QODTn,
QCKEn
tsu
002aab900
CK
mm
+ 1m + 2m + 3m + 4
DCSn
th
tPDM, tPDMSS
CK to Q
PAR_IN
th
tPHL, tPLH
CK to QERR
QERR(1)
output signal is dependent
on the prior unknown event
HIGH or LOW
unknown input event
tsu
CSGEN
RESET
data to QERR latency
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