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參數(shù)資料
| 型號： | SSTUB32868ET/S |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封裝： | 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 254K |
| 代理商： | SSTUB32868ET/S |
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SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
11 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
[1]
DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.
[2]
PAR_IN arrives one clock cycle after the data to which it applies.
[3]
This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
[4]
QERR0 is the previous state of output QERR.
[5]
If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on
the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus
two clock cycles or until RESET is driven LOW.
7.2 Functional information
The SSTUB32868 is a 28-bit 1 : 2 configurable registered buffer designed for 1.7 V to
1.9 V VDD operation.
All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All
outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error (QERR) output.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock, and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and
all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always
must be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be ensured between the two.
When entering reset, the register will be cleared and the data outputs will be driven LOW
quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
Table 5.
Parity and standby function table
Inputs
Output
RESET
DCS0[1]
CK
∑ of inputs = H
(D1 to D28)
PAR_IN[2]
HL
X
↑↓
even
L
H
HL
X
↑↓
odd
L
HL
X
↑↓
even
H
L
HL
X
↑↓
odd
H
HX
L
↑↓
even
L
H
HX
L
↑↓
odd
L
HX
L
↑↓
even
H
L
HX
L
↑↓
odd
H
HH
H
↑↓
XX
QERR0[5]
H
X
L or H
X
QERR0
L
X or floating
X
X or floating
H
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| SSTUB32870AHMLFT | 制造商:Integrated Device Technology Inc 功能描述:DDR2 REGISTER - Tape and Reel |
| SSTUB32871AHLF | 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUB32871AHLFT | 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUB32871AHMLF | 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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