參數(shù)資料
型號(hào): SSTUG32868ET/G
廠商: NXP SEMICONDUCTORS
元件分類: 鎖存器
英文描述: 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176
封裝: 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件頁(yè)數(shù): 1/29頁(yè)
文件大?。?/td> 166K
代理商: SSTUG32868ET/G
1.
General description
The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specically designed for use on two rank
by four (2R
× 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUG32868 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain QERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently
congured for high output drive strength. This allows use in high density designs with
heavier than normal net loading conditions. Furthermore, the SSTUG32868 features two
additional chip select inputs, which allow more versatile enabling and disabling in densely
populated memory modules. Both added features (drive strength and chip selects) are
fully backward compatible to the JEDEC standard register. Finally, the SSTUG32868 is
optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUG32868 is packaged in a 176-ball, 8
× 22 grid, 0.65 mm ball pitch, thin prole
ne-pitch ball grid array (TFBGA) package, which (while requiring a minimum
6mm
× 15 mm of board space) allows for adequate signal routing and escape using
conventional card technology.
2.
Features
I 28-bit data register supporting DDR2
I Fully compliant to JEDEC standard for SSTUB32868
I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2
× SSTUA32864 or 2 × SSTUA32866)
I Parity checking function across 22 input data bits
I Parity out signal
I Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
I Meets or exceeds SSTUB32868 JEDEC standard speed performance
I Supports up to 450 MHz clock frequency of operation
I Permanently congured for high output drive
I Optimized pinout for high-density DDR2 module design
I Chip-selects minimize power consumption by gating data outputs from changing state
SSTUG32868
1.8 V 28-bit 1 : 2 congurable registered buffer with parity for
DDR2-1G RDIMM applications
Rev. 01 — 23 April 2007
Product data sheet
相關(guān)PDF資料
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SSTV16859DGG,118 SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTUG32868ETS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
SSTUG32868G 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
SSTUH32864 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications
SSTUH32864EC 功能描述:寄存器 1.8V CONFIG REG BUFFER/DDRII RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTUH32864EC,518 功能描述:寄存器 1.8V CONFIG REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube