參數(shù)資料
型號(hào)： SSTUB32868ET/S
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176
封裝： 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件頁(yè)數(shù)： 1/30頁(yè)
文件大?。?/td> 254K
代理商： SSTUB32868ET/S
1.
General description
The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
by four (2R
× 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUB32868 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it can be
configured for normal or high output drive strength, simply by tying input pin SELDR either
HIGH or LOW as needed. This allows use in different module designs varying from low to
high density designs by picking the appropriate drive strength to match net loading
conditions. Furthermore, the SSTUB32868 features two additional chip select inputs,
which allow more versatile enabling and disabling in densely populated memory modules.
Both added features (drive strength and chip selects) are fully backward compatible to the
JEDEC standard register.
The SSTUB32868 is packaged in a 176-ball, 8
× 22 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum
6mm
× 15 mm of board space) allows for adequate signal routing and escape using
conventional card technology.
2.
Features and benefits
28-bit data register supporting DDR2
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2
× SSTUA32864 or 2 × SSTUA32866)
Parity checking function across 22 input data bits
Parity out signal
Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
Meets or exceeds SSTUB32868 JEDEC standard speed performance
Supports up to 450 MHz clock frequency of operation
Programmable for normal or high output drive
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
SSTUB32868
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for
DDR2-800 RDIMM applications
Rev. 04 — 22 April 2010
Product data sheet
相關(guān)PDF資料
PDF描述
SSTUG32865ET/S SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160
SSTUG32868ET/G 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176
SSTUP32866EC/S 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTV16857EC POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56
SSTV16859DGG,118 SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTUB32870AHMLFT 制造商:Integrated Device Technology Inc 功能描述:DDR2 REGISTER - Tape and Reel
SSTUB32871AHLF 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR)
SSTUB32871AHLFT 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR)
SSTUB32871AHMLF 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR)
SSTUB32872AHLF 功能描述:緩沖器和線路驅(qū)動(dòng)器 RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
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