參數(shù)資料
型號(hào)： SSTUB32868ET/S
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176
封裝： 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件頁(yè)數(shù)： 8/30頁(yè)
文件大?。?/td> 254K
代理商： SSTUB32868ET/S
SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
16 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
8.
Limiting values
[1]
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
This value is limited to 2.5 V maximum.
9.
Recommended operating conditions
[1]
The differential inputs must not be floating, unless RESET is LOW.
[2]
The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation.
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
0.5
+2.5
V
VI
input voltage
receiver
0.5
+2.5
V
VO
output voltage
driver
0.5
VDD +0.5
V
IIK
input clamping current
VI <0V or VI >VDD
-
±50
mA
IOK
output clamping current
VO <0V or VO >VDD
-
±50
mA
IO
output current
continuous; 0 V < VO < VDD
-
±50
mA
ICCC
continuous current through
each VDD or GND pin
-
±100
mA
Tstg
storage temperature
65
+150
°C
VESD
electrostatic discharge
voltage
Human Body Model (HBM); 1.5 k
Ω; 100 pF
2
-
kV
Machine Model (MM); 0
Ω; 200 pF
200
-
V
Table 7.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
1.7
-
2.0
V
Vref
reference voltage
0.49
× V
DD
0.50
× V
DD
0.51
× V
DD
V
VT
termination voltage
Vref 0.040 Vref
Vref + 0.040 V
VI
input voltage
0
-
VDD
V
VIH(AC)
AC HIGH-level input voltage
Dn, CSR and PAR_IN inputs
[1] Vref + 0.250 -
-
V
VIL(AC)
AC LOW-level input voltage
Dn, CSR and PAR_IN inputs
Vref 0.250 V
VIH(DC)
DC HIGH-level input voltage Dn, CSR and PAR_IN inputs
[1] Vref + 0.125 -
-
V
VIL(DC)
DC LOW-level input voltage
Dn, CSR and PAR_IN inputs
Vref 0.125 V
VIH
HIGH-level input voltage
RESET, CSGEN
[2] 0.65
× V
DD
--
V
VIL
LOW-level input voltage
RESET, CSGEN
-
0.35
× V
DD
V
VICR
common mode input voltage
range
CK, CK
0.675
-
1.125
V
VID
differential input voltage
CK, CK
600
-
mV
IOH
HIGH-level output current
SELDR either HIGH or LOW
-
8mA
IOL
LOW-level output current
SELDR either HIGH or LOW
-
8
mA
Tamb
ambient temperature
operating in free air
SSTUB32868ET/G
0
-
70
°C
SSTUB32868ET/S
0
-
85
°C
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