
41
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
May 1999
Sun Microsystems, Inc
Denitions of Idd Typical and Idd Maximum
The typical DC current values represent the current drawn at nominal voltage with a typical, busy computing
load. Variations in the device, computing load, and system implementation affect the actual current.
The maximum DC current values will rarely, if ever, be exceeded running all known computing loads over
the entire operating range. The maximum values are based on simulations.
Recommended Operating Conditions
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDC
Supply voltage (1.9 V) [1] (
±3%)
1. Even with the recommended bypass capacitance, there will be some dv/dt due to dynamic load variation. This 0-20 MHz dv/dt may be up to
100mV and is not included in the VDD requirements.
1.84
1.9
1.96
V
VDDPLL
Supply voltage (1.9 V) (
±3%)
1.84
1.9
1.96
V
VDDPE
CL
Supply voltage (1.9 V) (
±3%)
1.84
1.9
1.96
V
VDDPLL
2
Supply voltage (1.9 V) (
±3%)
1.84
1.9
1.96
V
VDDO
Supply voltage (1.9 V) (
±3%)
1.84
1.9
1.96
V
VDDH
Supply voltage (3.3v) (+/-5%)
3.14
3.3
3.47
V
VSSC
Core ground
–
0
–
V
VSSO
IO ground
–
0
–
V
VIH
High-level input
voltage
1.9 V signals
1.3
–
VDDC + 0.3
V
3.3 V non-PCI signals
2.4
–
VDDH + 0.3
V
3.3 V PCI signals
0.5(VDDH)
VDDH+0.5
V
VIL
Low-level input
voltage
1.9 V signals
-0.3
–
0.4
V
3.3 V non-PCI signals
-0.3
–
0.8
V
3.3 V PCI signals
-0.5
–
0.3VDDH
V
VCM
DC Common
Mode Input
Range
LVPECL clocks
see
VDDPECL
- 0.85
VDDPECL
- 0.5
VDDPECL
- 0.15
V
HSTL clocks
0.8
1.1
1.3
V
VDIFF
Minimum Input
Signal Amplitude
LVPECL clocks
see
± 0.155
0.35
–
V
HSTL clocks
± 0.25
–
V
IOH
High-level output current
-4.0
–
mA
IOL
Low-level output current
–
8.0
–
mA
TJ
Operating junction temperature
–
85
°C
TC
Operating case temperature
0
–
65 [2]
2. Refer to the SME5431PCI-360, SME5434PCI-440, SME5434PCI-480 module datasheet for thermal considerations.
°C