參數(shù)資料
型號(hào)： SME1430LGA-480
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587
封裝： CERAMIC, LGA-587
文件頁(yè)數(shù)： 24/60頁(yè)
文件大?。?/td> 646K
代理商： SME1430LGA-480
30
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
TIMING DIAGRAMS
L2-cache Read Hit in 2-2 Mode
Three consecutive reads are shown hitting the L2-cache in Figure 11. The control signal (TOE_L) and the
address for the tag read (ECAT) are shown in transition shortly after the rising edge of the
clock -- along with the control signal DOE_L and address for the data (ECAD). One cycle later, the data for
both the tag read and the data read is back at the pins of the CPU. The data arrives shortly before the next ris-
ing edge, meeting the set-up time and clock skew requirements. The data bus is eight bytes wide so the data
RAM is accessed twice for each data read request. The most critical eight bytes (D0_data1) of data are
returned rst followed by the next eight bytes (D0_data2) in the subsequent clock cycle. For each read request,
both the tag address and the tag data are stable for 2 clock cycles, but the data address and data read changes
every cycle. The reads are fully pipelined to allow full throughput.
.
Figure 11. Timing for L2-cache Read Hit (2-2 mode)
SRAM
012345
TSYN_WR_L
R0
R1
TOE_L
R0
R1
ECAT
A0_tag
A1_tag
TDATA
D0_tag
DSYN_
R0
R1
DOE_L
R0
ECAD
A0_data1 A0_data2 A1_data1
EDATA
D0_data1 D0_data2 D1_data1
CPU CLK
SRAM CLK
6
7
8
R1
R2
R1
R2
A2_tag
D1_tag
D2_tag
R1
R2
R1
R2
A1_data2 A2_data1 A2_data2
D1_data2 D2_data1 D2_data2
CYCLE
WR_L
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