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參數(shù)資料
| 型號： | SME1430LGA-480 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587 |
| 封裝： | CERAMIC, LGA-587 |
| 文件頁數(shù)： | 1/60頁 |
| 文件大小： | 646K |
| 代理商： | SME1430LGA-480 |
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DATA SHEET
1
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
UltraSPARC-II
i CPU
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
DESCRIPTION
The SME1430LGA CPU UltraSPARC-IIi microprocessor is a highly-integrated, 64-bit, SPARC V9 superscalar
processor. This second-generation UltraSPARC-IIi CPU includes the enhancements described on page 22 but
is otherwise identical to the SME1040 CPU. The optional APB (Advanced PCI Bridge, SME2411) increases
PCI connectivity and I/O bandwidth. The UltraSPARC-IIi interfaces have been optimized to satisfy many
uniprocessor system requirements. This balanced price-performance solution delivers the power and features
that a majority of high-end applications need.
The UltraSPARC-IIi CPU and the Advanced PCI Bridge enable designers to add UltraSPARC price-perfor-
mance levels to a broad range of embedded and desktop designs. This CPU-Bridge combination not only
optimizes embedded designs that require maximum processing power
such as telecommunications
devices, set-top boxes, high-end printers and photocopiers—but the UltraSPARC-IIi CPU also drives desktop
applications, supporting connection to a wide array of PCI-compatible devices up to 66 MHz (directly) and 33
MHz (across the bridge).
.
Features
SPARC V9 Architecture compliant
64-Byte block load and block store instructions
Binary Compatible with all SPARC application code
Supports software data prefetch into L2 cache
VIS Instruction Set (extended V9 instructions)
Supports up to 3 outstanding L2 cache misses
4-way superscalar design with 9 execution units
Supports UPA64S interface
- 4 integer execution units
- 960 megabyte/second (480 MHz CPU)
- 3 floating-point execution units
- 64-bit slave interface for graphics or similar subsystems
- 2 graphics execution units
Integrated PCI 2.1-compatible interface
Directly addresses little- or big-endian data
- Higher sustained PIO and DMA PCI I/O bandwidth than
competing solutions
64-bit address pointers
- Read prefetch and write gathering and posting
16-kilobyte non-blocking data cache
PCI DMA is cache-coherent
16-kilobyte instruction cache
- Dedicated TLB provides mapping and protection
- In-cache 2-bit branch prediction
JTAG Boundary Scan
- Single cycle branch following
Technology/Packaging
Integrated second level (L2) cache controller
- 0.25
m 5-layer metal CMOS process
Supports 0.25-megabyte to 2-megabyte cache sizes
- 1.9 V and 3.3 V (I/O Only) power supplies
Integrated control of 639 megabyte/second (at
480MHz) EDO DRAM memory subsystem
360, 440, and 480 MHz speed grades
May 1999
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