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參數(shù)資料
| 型號： | SME5410MCZ-270 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 270 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 183K |
| 代理商： | SME5410MCZ-270 |
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SME5410MCZ-270
UltraSPARC
-IIi CPU Module
270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
DESCRIPTION
The UltraSPARC-IIi CPU module (SME5410MCZ-270) is a high performance, SPARC
V9-compliant, small
form-factor CPU module. It interfaces to the UltraSPARC Port Architecture 64S (UPA64S) interconnect bus,
main memory, and the primary PCI bus.
The module consists of one UltraSPARC-IIi microprocessor, one 32K x 36 tag SRAM, two 32K x 36 data
SRAMs, and circuitry for generating the processor, UPA64S clocks. PCI clocks are generated externally.
Components on the module operate at nominal voltages of 3.3V and 2.6V. All signal levels to and from the
module are 3.3V LVTTL compatible, with the exception of the following: both the differential UPA clock out-
puts, which operate at 3.3V, PECL; and the PCI interface signals, which are 3.3V PCI compatible.
The module runs at 270 MHz internal processor frequency. Clock synthesizer and division circuitry on the
module set the UPA frequency to one third of the internal processor frequency. The module interface is imple-
mented using two high-speed, controlled-impedance connectors, see the "Module Block Diagram" on page 2.
Features
Benets
High performance UltraSPARC-II
i CPU module
8.5 SPECint95 (est.), 10.1 SPECfp95 (est.) at 270 MHz
Programmable bus speed
Provides the exibility for using the CPU at different bus
speeds
SPARC
V9 compliant
Run applications that conform to the SPARC
V9 ABI
Implements VIS Instruction Set (VIS
)
Comprehensive hardware support for 3D graphics,
H-261 compression/decompression, and MPEG2
decompression
64-bit wide data bus
Peak bandwidth of up to 1.2 Gbyte
0.5 Mbyte E-cache clocked at 150 MHz
UltraSPARC-II
i CPU module pipelined E-cache
interface delivers high performance
Operates at 3.3V and 2.6V LVTTL
Very high bus speeds and power savings, thus reducing
the heat generated
66 MHz PCI bus to rev. 2.1 PCI specication
Integrated interface simplies PCI system design
130 mm x 100 mm form factor
Small footprint, modular manufacturing
JTAG (IEEE 1149) boundary-scan interface
Board-level testability
System interface through two impedance-controlled
connectors
High performance impedance controlled connectors
provide reliable signal integrity.
July 1998
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