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Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces

UltraSPARC-IIi CPU

SME1430LGA-360

SME1430LGA-440

SME1430LGA-480

May 1999

Sun Microsystems, Inc

Load/Store Unit (LSU)

The LSU is responsible for generating the virtual address of all loads and stores (including atomics and ASI

loads), for accessing the data cache, for decoupling load misses from the pipeline through the load buffer, and

for decoupling the stores through a store buffer. One load or one store can be issued per cycle. The store buffer

can compress (or gather) multiple stores to the same 8 bytes into a single L2-cache access. The UPA64S and

PCI control units can compress sequential 8-byte stores into burst transactions, to improve noncacheable store

bandwidth.

Phase Locked Loops (PLL)

To minimize the clock skew at the system level the UltraSPARC-IIi CPU has PLLs for both the processor clock

and the PCI clock. The internal PCI clock runs at twice the speed of the PCI interface clock. For details, see

Signals

All external SRAM signals are of 1.9 V magnitude and typically exist only on the processor module. All other

signals are 3.3 V LVTTL. When a module is employed , the clock frequencies handled by the system board are

at most 120 MHz, making system-board designs easier than module designs. The highest signal frequency

from the module to the motherboard is 75 MHz. (unless the 120 MHz UPA64S interface is used), which allows

economic motherboard design.

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