參數(shù)資料
型號(hào)： SME1430LGA-480
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 480 MHz, RISC PROCESSOR, CBGA587
封裝： CERAMIC, LGA-587
文件頁(yè)數(shù)： 12/60頁(yè)
文件大小： 646K
代理商： SME1430LGA-480
2
SME1430LGA-360
SME1430LGA-440
SME1430LGA-480
Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces
UltraSPARC-IIi CPU
May 1999
Sun Microsystems, Inc
The UltraSPARC-IIi product range encompasses two generations of processor represented by a difference in
core operating voltage. The following table lists this range of processor and associated module products by
operating frequency. In this table, thick borders surround references to products described in this datasheet.
The SME1430LGA-480 (with a 2-megabyte cache) achieves estimated SPECint95 and SPECfp95 benchmarks
of 20.2 and 22.5, respectively. At the same time, it provides industry-leading bandwidth and latency. The
UltraSPARC-IIi CPU has integrated a memory controller and the I/O interfaces into the microchip.
Figure 1 shows a high-level illustration of an SME1430LGA-based system. This system minimizes the mem-
ory-to-CPU bottleneck by using the following interface speeds:
As shown in "Product System and Subsystems" beginning on page 23, this solution supports a wide array of
applications.
Each functional area on the SME1430LGA maintains decentralized control, allowing many activities to over-
lap. Sustained performance of up to 4 instructions per cycle is supported (even in the presence of conditional
branches and cache misses) by a decoupled Prefetch and Dispatch Unit. Load buffers on the input side of the
Execution Unit, together with store buffers on the output side, decouple pipeline execution from data cache
misses. Instructions predicted to be executed are issued in program order to multiple functional units. Such
instructions are executed in parallel and may be completed out of order. The separate Memory Control and
PCI I/O interface units also decouple their related key activities from the instruction pipeline.
The UltraSPARC-IIi CPU supports the VIS extended instruction set for the V9 architecture. Use of VIS in con-
junction with the four-way superscalar pipeline on the i-series processors enhances the performance for a
wide range of networking applications, including TCP/IP. Use of VIS instructions also enables speed-up of
I/O operations.
IIi Product Family
Frequency
(MHz)
First Generation “Sabre” [1] (2.6 V core)
1. “Sabre” and “Sapphire Red” are Sun internal names. Use marketing part numbers for orders and enquiries.
Second Generation “Sapphire Red” [1] (1.9 V core)
CPU
Module (L2-cache, bytes)
CPU
Module (L2-cache, bytes)
270
SME1040CGA-270
SME5410MCZ-270 (256 kB)
NA (not available)
NA
300
SME1040CGA-300
SME5421MCZ-300 (512 kB)
NA
333
SME1040CGA-333
SME5421MCZ-333 (2 MB)
NA
360
NA [2]
2. The 360 MHz sabre processor is only available within a CPU module.
SME5421MCZ-360 (2 MB)
SME1430LGA-360
SME5431PCI-360 (256 kB)
440
NA
SME1430LGA-440
SME5434PCI-440 (2 MB)
480
NA
SME1430LGA-480
SME5434PCI-480 (2 MB)
Hardware Interface
360 MHz CPU
440 MHz CPU
480 MHz CPU
Unit
CPU
360
440
480
MHz
SRAM
external cache (L2 or E-cache)
180
220
240
MHz
DRAM data throughput
90
88
80
MHz
PCI
up to 66
MHz
相關(guān)PDF資料
PDF描述
SME1701-BGA133 32-BIT, 133 MHz, MICROPROCESSOR, PBGA316
SME5224AUPA-360 64-BIT, 360 MHz, RISC PROCESSOR
SME5410MCZ-270 64-BIT, 270 MHz, RISC PROCESSOR, XMA
SME5434PCI-440 64-BIT, 440 MHz, RISC PROCESSOR, XMA
SME5434PCI-480 64-BIT, 480 MHz, RISC PROCESSOR, XMA
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