參數(shù)資料
型號: SM34020AHTM32
廠商: TEXAS INSTRUMENTS INC
元件分類: 圖形處理器
英文描述: GRAPHICS PROCESSOR, CQFP132
封裝: CERAMIC, QFP-132
文件頁數(shù): 75/98頁
文件大?。?/td> 1546K
代理商: SM34020AHTM32
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
77
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
host-interface-cycle timing (block-read cycle) (see Notes 5 and 9 and Figure 45)
NO
34020A-32
34020A-40
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
26
tw(RDH)
Pulse duration, HREAD high
28
25
ns
30
tw(RDL)
Pulse duration, HREAD low
18
15
ns
37
tsu(RDH-CK2L)
Setup time, HREAD high to LCLK2 no longer high,
prefetch read mode
30
25
ns
39
td(CK1H-RYH)
Delay time, LCLK1 no longer low to HRDY high
tQ+20
tQ+18
ns
40
td(RDH-RYL)
Delay time, HREAD or HCS high to HRDY low
20
18
ns
41
td(CK2L-STL)
Delay time, LCLK2 no longer high to HDST low
tQ+15+s
tQ+13.5+ s
ns
42
td(CK1L-STH)
Delay time, LCLK1 no longer high to HDST high
tQ+15
tQ+13.5
ns
43
tsu(STL-RYH)
Setup time, HDST low to HRDY no longer low
tQ--15
tQ--13.5
ns
44
td(RYH-STH)
Delay time, HRDY no longer low to HDST high
2tQ+15
2tQ+13.5
ns
45
td(RDL-RYH)
Delay time, HREAD or HCS low to HRDY high after
prefetch
25
20
ns
50
th(STH-CTV)
Hold time, CAS,TR/QE, DDIN valid after HDST high
-- 2
ns
Setup time to ensure recognition of input on this clock edge. When the SMJ34020A is set for block reads, the deassertion of HREAD is used
to request a local memory cycle at the next sequential address location.
NOTES: 5. s =tQ if using the clock stretch;
s = 0 otherwise
9. Although HCS, HREAD, and HWRITE can be totally asynchronous to the SMJ34020A, cycle responses to the signals are
determined by local memory cycles.
HDST
HRDY
HREAD
HCS
LCLK2
LCLK1
43
40
37
42
26
39
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
45
41
44
40
26
37
30
See clock stretch, page 21.
CAS
TR/QE
DDIN
50
Figure 45. Host-Interface-Cycle Timing (Block-Read Cycle)
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