參數(shù)資料
型號(hào)： SM34020AHTM32
廠商： TEXAS INSTRUMENTS INC
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, CQFP132
封裝： CERAMIC, QFP-132
文件頁(yè)數(shù)： 68/98頁(yè)
文件大?。?/td> 1546K
代理商： SM34020AHTM32
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
70
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
CLKIN and RESET timing requirements (see Figure 40)
NO
SMJ34020A-32
34020A-40
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
1
tc(CKI)
Cycle time, period of CLKIN (4tQ)
31.25
50
25
50
ns
2
tw(CKIH)
Pulse duration, CLKIN high
10
8
ns
3
tw(CKIL)
Pulse duration, CLKIN low
10
8
ns
4
tt(CKI)
Transition time, CLKIN
2*
5*
2
5*
ns
5
th(CKI-RSL)
Hold time, RESET low after CLKIN high
15
12
ns
6
tsu(RSH-CKI)
Setup time, RESET high to CLKIN no longer
low
10
6
ns
7
t
Pulse duration, Initial reset during powerup
160tQ -- 40
ns
7
tw(RSL)
Pulse duration,
RESET low
Reset during active operation
16tQ -- 40
ns
8
tsu(CSL-RSH)
Setup time, HCS low to RESET high to
configure self-bootstrap mode
8tQ+55
ns
9
td(CSH-RSH)
Delay time, HCS no longer low to RESET high
to configure self-bootstrap mode
4tQ -- 50§
ns
10
tw(CSL)
Pulse duration, HCS low to configure GSP in
self-bootstrap mode
4tQ+55
ns
These timings are required only to synchronize the SMJ34020A to a particular quarter cycle.
The initial reset pulse on powerup must remain valid until all internal states have been initialized. Resets applied after the SMJ34020A has been
initialized need to be present only long enough to be recognized by the internal logic; the internal logic maintains an internal reset until all internal
states have been initialized (34 LCLK1 cycles).
§ Parameter 9 is the maximum amount by which the RESET low-to-high transition can be delayed after the start of the HCS low-to-high transition
and still assure that the SMJ34020A is configured to run in the self-bootstrap mode (HLT bit = 0) following the end of reset.
* The parameter is not production tested.
2
1
3
4
5
6
7
8
9
10
CLKIN
RESET
HCS
Figure 40. CLKIN and RESET Timing Requirements
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