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參數資料
| 型號： | SM34020AHTM32 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, CQFP132 |
| 封裝： | CERAMIC, QFP-132 |
| 文件頁數： | 58/98頁 |
| 文件大?。?/td> | 1546K |
| 代理商： | SM34020AHTM32 |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
61
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
cycle timing examples (continued)
Data transfer from memory to a coprocessor requires an initialization cycle to inform the coprocessor what is
to be transferred and then a memory cycle to perform the actual transfer (Figure 34). The coprocessor can place
status information on LAD during the initialization cycle for the SMJ34020A. Two types of
memory-to-coprocessor instructions are supported: one provides a count (from 1 to 32) of data to be moved
in the instruction; the other specifies a register in the SMJ34020A to be used for the count. Both instructions
specify a register to be used as an index into memory. The index can be postincremented or predecremented
on each transfer cycle.
GI
LAD
Command
Address
ALTCH
RAS
WE
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
R1
Q2
Q3
Q1
CAMD
CAS
TR/QE
SF
DDIN
DDOUT
R0
Data 1
PGMD
SIZE16
LRDY
BUSFLT
RCA
LAD
Data 2
2nd Column
1st Column
Row
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
(TMS34020A)
(memory)
Command Cycle
Address
Data Tansfer
Data Transfer
Q4
(see Note A)
(see Note B)
See clock stretch, page 21.
NOTES: A. LAD (SMJ34020A): Output to LAD by the SMJ34020A
LAD (memory):
Output to LAD by the memory
Command:
Coprocessor ID, instruction and status code present on LAD
Address:
Memory address for the data transfer with coprocessor status code
Data n:
Data to or from the coprocessor (number of values transferred depends on a value in a register or count in
the instruction)
B. All coprocessor cycles are implemented as 32-bit operations; therefore SIZE16 should be high during these cycles.
Figure 34. Transfer Memory to Coprocessor Register(s)
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