
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
71
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
local-bus timing: output clocks (see Note 5 and Figure 41)
NO
SMJ34020A-32
34020A-40
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
11
tc(LCK)
Cycle time, period of local clocks LCLK1,
LCLK2
4tc(CKI)+ s*
ns
12
tw(LCKH)
Pulse duration, local clock high
2tQ--15
2tQ--13.5
ns
12a
tw(LCKH)
Pulse duration, LCLK1 high (see Note 6)
2tQ--10
2tQ--7
ns
13
tw(LCKL)
Pulse duration, local clock low
2tQ--15+ s
2tQ--13.5+ s
ns
13a
tw(LCKL)
Pulse duration, LCLK1 low (see Note 6)
2tQ--10+ s
2tQ--7+ s
ns
14
tt(LCK)
Transition time, LCLK1 or LCLK2
15
13.5
ns
15
th(CK1H-CK2L)
Hold time, LCLK2 low after LCLK1 high
tQ--15
tQ--13.5
ns
16
th(CK2H-CK1H)
Hold time, LCLK1 high after LCLK2 high
tQ--15
tQ--13.5
ns
17
th(CK1L-CK2H)
Hold time, LCLK2 high after LCLK1 low
tQ--15
tQ--13.5
ns
18
th(CK2L-CK1L)
Hold time, LCLK1 low after LCLK2 low
tQ--15+ s
tQ--13.5+ s
ns
19
th(CK1H-CK2H)
Hold time, LCLK2 high after LCLK1 high
3tQ--15
3tQ--13.5
ns
20
th(CK2H-CK1L)
Hold time, LCLK1 low after LCLK2 high
3tQ--15+ s
3tQ--13.5+ s
ns
21
th(CK1L-CK2L)
Hold time, LCLK2 low after LCLK1 low
3tQ--15+ s
3tQ--13.5+ s
ns
22
th(CK2L-CK1H)
Hold time, LCLK1 high after LCLK2 low
3tQ--15+ s
3tQ--13.5+ s
ns
This parameter can also be specified as 4tQ.
* The parameter is not production tested.
NOTES: 5. s =tQ if using the clock stretch;
s = 0 otherwise
6. Parameters 12a and 13a are specified with 1.5 V timing levels (parameters 12 and 13 are specified with standard timing voltage
levels).
LCLK1
LCLK2
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
14
11
12
13
19
21
22
15
16
17
18
11
12
13
14
20
12a
13a
NOTE A: Although LCLK1 and LCLK2 are derived from CLKIN, no timing relationship between CLKIN and the local clocks is to be assumed,
except the period of the local clocks is four times the period of CLKIN.
Figure 41. Local-Bus Timing: Output Clocks