參數(shù)資料
型號(hào)： SM320C30HFGM50
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 50 MHz, OTHER DSP, CQFP196
封裝： NONCONDUCTIVE TIE BAR, CERAMIC, QFP-196
文件頁數(shù)： 33/48頁
文件大?。?/td> 874K
代理商： SM320C30HFGM50
SMJ320C30
DIGITAL SIGNAL PROCESSOR
SOURCED FROM: SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
timer pin (TCLK0 and TCLK1) timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following table defines the timing parameters for the timer pin.
timing parameters for timer pin (TCLK0 and TCLK1) (see Figure 29)
NO
320C30-40
320C30-50
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
99
tsu(TCLK-H1L)
Setup time,
TCLK ext
before H1 low
TCLK ext
10
8
ns
100
th(TCLK-H1L)
Hold time,
TCLK ext after
H1 low
TCLK ext
0
ns
101
td(TCLK-H1H)
Delay time, H1
high to TCLK
int valid
TCLK int
9
ns
102
t
Cycle time,
TCLK ext
tc(H) × 2.6*
ns
102
tc(TCLK)
Cycle time,
TCLK
TCLK int
tc(H) × 2
tc(H) × 232*
tc(H) × 2
tc(H) × 232*
ns
103
t
Pulse duration,
TCLK ext
tc(H) + 12*
tc(H) + 10*
ns
103
tw(TCLK)
Pulse duration,
TCLK high/low
TCLK int
[tc(TCLK)/2]--5
[tc(TCLK)/2]+5
[tc(TCLK)/2]--5
[tc(TCLK)/2]+5
ns
Numbers in this column are used in Figure 29.
Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous
input clock.
* This parameter is not production tested.
101
100
H1
H3
99
Timer
Pin
103
102
NOTE A: Period and polarity of valid logic level are specified by contents of internal control registers.
Figure 29. Timing for Timer Pin
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PDF描述
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