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參數(shù)資料
| 型號： | SM320C30HFGM50 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 50 MHz, OTHER DSP, CQFP196 |
| 封裝： | NONCONDUCTIVE TIE BAR, CERAMIC, QFP-196 |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 874K |
| 代理商： | SM320C30HFGM50 |
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SMJ320C30
DIGITAL SIGNAL PROCESSOR
SOURCED FROM: SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 25 occurs; otherwise, an additional delay of one clock cycle is
possible.
The “timing parameters for HOLD/HOLDA” table defines the timing parameters for the HOLD and HOLDA
signals.
The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, allowing
the processor to continue until a second write is encountered.
HOLD/HOLDA timing (see Figure 25)
NO
320C30-40
320C30-50
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
80
tsu(HOLD)
Setup time, HOLD before H1 low
13
10
ns
81
tv(HOLDA)
Valid time, HOLDA after H1 low
0*
9
0*
7
ns
82
tw(HOLD)
Pulse duration, HOLD low
2tc(H)
ns
83
tw(HOLDA)
Pulse duration, HOLDA low
tc(H)--5*
ns
84
td(H1L-SH)H
Delay time, H1 low to STRB high for a HOLD
0*
9*
0*
7*
ns
85
tdis(H1L-S)
Disable time, H1 low to STRB high impedance
0*
9*
0*
8*
ns
86
ten(H1L-S)
Enable time, H1 low to STRB active
0*
9*
0*
7*
ns
87
tdis(H1L-RW)
Disable time, H1 low to R/W high impedance
0*
9*
0*
8*
ns
88
ten(H1L-RW)
Enable time, H1 low to R/W active
0*
9*
0*
7*
ns
89
tdis(H1L-A)
Disable time, H1 low to address high impedance
0*
9*
0*
8*
ns
90
ten(H1L-A)
Enable time, H1 low to address valid
0*
13*
0*
12*
ns
91
tdis(H1H-D)
Disable time, H1 high to data high impedance
0*
12*
0*
8*
ns
Numbers in this column are used in Figure 25.
* This parameter is not production tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SM320C31GFM27 | 32-BIT, 27 MHz, OTHER DSP, CPGA141 |
| SM320C30HUM25 | 32-BIT, 25 MHz, OTHER DSP, CQFP196 |
| SM320C30HTM28 | 32-BIT, 28 MHz, OTHER DSP, CQFP196 |
| SM320C30HFGM25 | 32-BIT, 25 MHz, OTHER DSP, CQFP196 |
| SM320C30HFGM28 | 32-BIT, 28 MHz, OTHER DSP, CQFP196 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SM320C31 WAF | 制造商:Texas Instruments 功能描述: |
| SM320C31GFAM40 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| SM320C31GFAM50 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 50MHZ 25MIPS 141CPGA - Trays |
| SM320C31GFAS60 | 制造商:Texas Instruments 功能描述:3RD GENERATION DSP, 60 MHZ - Trays |
| SM320C31HFGM40 | 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 40MHZ 20MIPS 132CFPAK - Trays |
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