參數(shù)資料
型號: SM320C30HFGM50
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 50 MHz, OTHER DSP, CQFP196
封裝: NONCONDUCTIVE TIE BAR, CERAMIC, QFP-196
文件頁數(shù): 25/48頁
文件大?。?/td> 874K
代理商: SM320C30HFGM50
SMJ320C30
DIGITAL SIGNAL PROCESSOR
SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal.
timing parameters for IACK (see Figure 22)
NO
320C30-40
320C30-50
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
63
td(H1H-IACKL)
Delay time, H1 high to IACK low
9
7
ns
64
td(H1H-IACKH)
Delay time, H1 high to IACK high
9
7
ns
Numbers in this column match those used in Figure 22.
H3
H1
IACK
Address
Data
63
64
Fetch IACK
Instruction
IACK
Data Read
Figure 22. Timing for Interrupt-Acknowledge (IACK)
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