- 您現(xiàn)在的位置：買賣IC網 > PDF目錄98082 > SM320C30HFGM50 (TEXAS INSTRUMENTS INC) 32-BIT, 50 MHz, OTHER DSP, CQFP196 PDF資料下載
參數(shù)資料
| 型號： | SM320C30HFGM50 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 50 MHz, OTHER DSP, CQFP196 |
| 封裝： | NONCONDUCTIVE TIE BAR, CERAMIC, QFP-196 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 874K |
| 代理商： | SM320C30HFGM50 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
SMJ320C30
DIGITAL SIGNAL PROCESSOR
SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
interrupt-response timing
The following table defines the timing parameters for the INT signals.
timing parameters for INT3--INT0 [Q = tc(H)] (see Figure 21)
NO
320C30-40
320C30-50
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
61
tsu(INT)
Setup time, INT3--INT0 before H1 low
13
10
ns
62
tw(INT)
Pulse duration, INT3--INT0, to assure only one interrupt seen
Q <2Q*
ns
* This parameter is not production tested.
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
SMJ320C30 interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
D
A minimum of one H1 falling edge
D
No more than two H1 falling edges
The SMJ320C30 can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 21 occurs; otherwise, an additional delay
of one clock cycle is possible.
Reset or
Interrupt
Vector
Read
H3
H1
INT3--INT0
Pins
INT3--INT0
Flag
Data
Vector Address
First
Instruction
Address
61
Fetch First
Instruction of
Service Routine
62
Addr
Figure 21. Timing for INT3--INT0 Response [Q=tc(H)]
相關PDF資料 |
PDF描述 |
|---|---|
| SM320C31GFM27 | 32-BIT, 27 MHz, OTHER DSP, CPGA141 |
| SM320C30HUM25 | 32-BIT, 25 MHz, OTHER DSP, CQFP196 |
| SM320C30HTM28 | 32-BIT, 28 MHz, OTHER DSP, CQFP196 |
| SM320C30HFGM25 | 32-BIT, 25 MHz, OTHER DSP, CQFP196 |
| SM320C30HFGM28 | 32-BIT, 28 MHz, OTHER DSP, CQFP196 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SM320C31 WAF | 制造商:Texas Instruments 功能描述: |
| SM320C31GFAM40 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| SM320C31GFAM50 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 50MHZ 25MIPS 141CPGA - Trays |
| SM320C31GFAS60 | 制造商:Texas Instruments 功能描述:3RD GENERATION DSP, 60 MHZ - Trays |
| SM320C31HFGM40 | 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 40MHZ 20MIPS 132CFPAK - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。