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參數(shù)資料
| 型號： | SM320C30HFGM50 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 50 MHz, OTHER DSP, CQFP196 |
| 封裝： | NONCONDUCTIVE TIE BAR, CERAMIC, QFP-196 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 874K |
| 代理商： | SM320C30HFGM50 |
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SMJ320C30
DIGITAL SIGNAL PROCESSOR
SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 20 occurs; otherwise, an additional delay of one clock cycle can
occur. R/W and XR/W are in the high-impedance state during reset and can be provided with a resistive pullup,
nominally 18 k to 22 k, to prevent spurious writes from occurring. The asynchronous reset signals include
XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. HOLD is an asynchronous input and
can be asserted during reset.
Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states
and, therefore, results in slow external accesses until these registers are initialized.
timing parameters for RESET [P = tc(CI)] (see Figure 9 and Figure 20)
NO
320C30-40
320C30-50
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
50
tsu(RESET)
Setup time, RESET before CLKIN low
10
P*
10
P*
ns
51
td(CLKINH-H1H)
Delay time, CLKIN high to H1 high
2
14
2
10
ns
52
td(CLKINH-H1L)
Delay time, CLKIN high to H1 low
2
14
2
10
ns
53
tsu(RESETH-H1L)
Setup time, RESET high beforeH1 low after ten H1 clock
cycles
9
7
ns
54
td(CLKINH-H3L)
Delay time, CLKIN high to H3 low
2
14
2
10
ns
55
td(CLKINH-H3H)
Delay time, CLKIN high to H3 high
2
14
2
10
ns
56
tdis(H1H-XD)
Disable time, H1 high to (X)D high-impedance state
15*
12*
ns
57
tdis(H3H-XA)
Disable time, H3 high to (X)A high-impedance state
9*
8*
ns
58
td(H3H-CONTROLH)
Delay time, H3 high to control signals high
9*
8*
ns
59
td(H1H-IACKH)
Delay time, H1 high to IACK high
9*
8*
ns
60
tdis(RESETL-ASYNCH)
Disable time, RESET low to asynchronous reset signals in
the high-impedance state
21*
17*
ns
See Figure 9 for temperature dependence for the 40-MHz SMJ320C30.
* This parameter is not production tested.
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相關(guān)代理商/技術(shù)參數(shù) |
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| SM320C31 WAF | 制造商:Texas Instruments 功能描述: |
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