參數(shù)資料
型號(hào): SM320C30HFGM50
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-BIT, 50 MHz, OTHER DSP, CQFP196
封裝: NONCONDUCTIVE TIE BAR, CERAMIC, QFP-196
文件頁數(shù): 31/48頁
文件大小: 874K
代理商: SM320C30HFGM50
SMJ320C30
DIGITAL SIGNAL PROCESSOR
SOURCED FROM: SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and the reverse.
timing parameters for peripheral pin changing from general-purpose output to input mode
(see Note 12 and Figure 27)
NO
320C30-40
320C30-50
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
95
th(H1H)
Hold time after H1 high
13
10
ns
96
tsu(GPIOH1L)
Setup time, peripheral pin before H1 low
9
ns
97
th(GPIOH1L)
Hold time, peripheral pin after H1 low
0
ns
Numbers in this column are used in Figure 27.
NOTE 12: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined
by the contents of internal control registers associated with each peripheral.
97
96
95
Value on
Terminal Seen in
Peripheral
Control Register
Synchronizer Delay
Buffers Go
From Output to
Input
Execute Store
of Peripheral
Control
Register
Data Bit
I/O
Control Bit
H1
H3
Output
Data
Seen
Data Sampled
Peripheral
Pin
Figure 27. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
相關(guān)PDF資料
PDF描述
SM320C31GFM27 32-BIT, 27 MHz, OTHER DSP, CPGA141
SM320C30HUM25 32-BIT, 25 MHz, OTHER DSP, CQFP196
SM320C30HTM28 32-BIT, 28 MHz, OTHER DSP, CQFP196
SM320C30HFGM25 32-BIT, 25 MHz, OTHER DSP, CQFP196
SM320C30HFGM28 32-BIT, 28 MHz, OTHER DSP, CQFP196
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