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參數(shù)資料
| 型號(hào)： | SII3114CTU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 99/127頁(yè) |
| 文件大小： | 564K |
| 代理商： | SII3114CTU |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
65
SiI-DS-0103-D
Channel X Extended Task File Register – Command Buffering
Address Offset: 98H / D8H / 298H / 2D8H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Cylinder High Ext
Cylinder Low Ext
Start Sector Ext
Sector Count Ext
This register defines one of the IDE Channel X Task File registers used for Command Buffered accesses in the
SiI3114. The register bits are defined below. If this register is written, the IDE Channel X Task File Device+Head
byte of the IDE Channel X Task File Register 1 – Command Buffering register must not be written.
Bit [31:24]: Task File Cylinder High Ext(R/W). This write-only bit field defines the Channel X Task File
Extended Cylinder High register.
Bit [23:16]: Task File Cylinder Low Ext (R/W). This bit field defines the Channel X Task File Extended
Cylinder Low register.
Bit [15:08]: Task File Start Sector Ext (R/W). This bit field defines the Channel X Task File Extended Start
Sector register.
Bit [07:00]: Task File Sector Count Ext (R/W). This bit field defines the Channel X Task File Extended
Sector Count register.
Channel X Virtual DMA/PIO Read Ahead Byte Count
Address Offset: 9CH / DCH / 29CH / 2DCH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Virtual DMA/PIO Read Ahead Byte Count
Not
Us
e
d
This register defines the read ahead byte count register for Virtual DMA and PIO Read Ahead transfers on
Channel X in the SiI3114. In Virtual DMA mode (PCI bus master DMA with PIO transfers), all 32 bits are used as
the word-aligned byte count. In PIO Read Ahead mode, only the lower 16 bits are used as the word-aligned byte
count.
Channel X Task File Configuration + Status
Address Offset: A0H / E0H / 2A0H / 2E0H
Access Type: Read/Write
Reset Value: 0x6515_0101
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
R
e
served
Watchdog
Int
Ena
Watchdog
Ena
Watchdog
Timeout
Interrupt
Status
V
irtua
lDMA
Int
Reserved
Cha
nne
lRs
t
Buffe
re
d
Cmd
R
e
served
This register defines the task file configuration and status register for Channel X in the SiI3114. The register bits
are defined below.
Bit [31:16]: Reserved (R). This bit field is reserved and defaults to 0x6515.
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