參數(shù)資料
型號： SII3114CTU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP176
封裝： TQFP-176
文件頁數(shù)： 94/127頁
文件大?。?/td> 564K
代理商： SII3114CTU
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
61
SiI-DS-0103-D
FIFO Pointers1– Channel X
Address Offset: 68H / 78H / 268H / 278H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
FIFO Byte 1 Wr Pointer
FIFO Byte 1 Rd Pointer
FIFO Byte 0 Wr Pointer
FIFO Byte 0 Rd Pointer
This register provides visibility into the data FIFO for Channel X in the SiI3114. The data FIFO is organized as a
four byte-wide x 64 deep memory array. There are separate write and read pointers for each of the byte slices.
This register is used for hardware debugging purposes only. The register bits are defined below.
Bit [31:24]: FIFO Byte 1 Wr Pointer (R). This bit field provides the write pointer for Byte 1.
Bit [23:16]: FIFO Byte 1 Rd Pointer (R). This bit field provides the read pointer for Byte 1.
Bit [15:08]: FIFO Byte 0 Wr Pointer (R). This bit field provides the write pointer for Byte 0.
Bit [07:00]: FIFO Byte 0 Rd Pointer (R). This bit field provides the read pointer for Byte 0.
FIFO Pointers2– Channel X
Address Offset: 6CH / 7CH / 26CH / 27CH
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
FIFO Byte 3 Wr Pointer
FIFO Byte 3 Rd Pointer
FIFO Byte 2 Wr Pointer
FIFO Byte 2 Rd Pointer
This register provides visibility into the data FIFO for Channel X in the SiI3114. The data FIFO is organized as a
four byte-wide x 64 deep memory array. There are separate write and read pointers for each of the byte slices.
This register is used for hardware debugging purposes only. The register bits are defined below.
Bit [31:24]: FIFO Byte 3 Wr Pointer (R). This bit field provides the write pointer for Byte 3.
Bit [23:16]: FIFO Byte 3 Rd Pointer (R). This bit field provides the read pointer for Byte 3.
Bit [15:08]: FIFO Byte 2 Wr Pointer (R). This bit field provides the write pointer for Byte 2.
Bit [07:00]: FIFO Byte 2 Rd Pointer (R). This bit field provides the read pointer for Byte 2.
相關(guān)PDF資料
PDF描述
SII3124ACBHU PCI BUS CONTROLLER, PBGA364
SII3512ECTU128 PCI BUS CONTROLLER, PQFP128
SII3531ACNU PCI BUS CONTROLLER, QCC48
SIO10N268-NU MULTIFUNCTION PERIPHERAL, PQFP128
SIS300 GRAPHICS PROCESSOR, PBGA365
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII3124A 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3124ACBHU 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3132 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller
SII3132CNU 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN
SII3512 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*