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參數(shù)資料
| 型號(hào)： | SII3114CTU |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 87/127頁(yè) |
| 文件大小： | 564K |
| 代理商： | SII3114CTU |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
54
2007 Silicon Image, Inc.
Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from Channel X to system memory. This bit is cleared to specify a DMA read operation from
system memory to the Channel X device.
Bit [02]: Reserved (R). This bit is reserved and returns zero on a read.
Bit [01]: Interrupt Steering (R/W). This bit is set to 1 to allow interrupts from all four channels. If the bit is a
0 (the default), only interrupts from the channel selected by the “shadow” Device Select bit are enabled.
This bit appears only in the Channel 2 (offset 200H) register; this bit is reserved in the Channel 0 (offset
00H), Channel 1 (offset 08H), and Channel 3 (offset 208H) registers.
Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – Channel X. This bit is set to enable PCI bus
master operations for Channel X. PCI bus master operations can be halted by clearing this bit, but will
erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the
operation will be aborted and the data discarded. While this bit is set, accessing Channel X Task File or
PIO data registers will be terminated with Target-Abort.
PRD Table Address – Channel X
Address Offset: 04H / 0CH / 204H / 20CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address
R
e
served
This register defines the PRD Table Address register for Channel X in the SiI3114. The register bits are defined
below.
Bit [31:02]: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines
the Descriptor Table base address.
Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
PCI Bus Master2 – Channel X
Address Offset: 10H / 18H / 210H / 218H
Access Type: Read/Write
Reset Value: 0x0808_XX00 (Chnl 0/2) / 0x0008_0000 (Chnl 1/3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Chnl
X+
1
PB
M
Simplex
Chnl
X+
1
P
B
M
DMA
Ca
p
0
Chnl
X+
1
P
B
M
DMA
Ca
p
1
Chnl
X+
1
Watchdog
Chnl
X+
1
Buffe
rE
m
pty
Chnl
X+
1
DMA
Comp
Chnl
X+
1
PBM
Error
Chnl
X+
1
P
B
M
Ac
ti
v
e
Watchdog
Chnl
X+
1
DMA
Comp
Software
R
eserved
SA
TA
IN
T
X+
1
R
eserved
Reserved for Chnl 1/3
Chnl
X
PB
M
Simplex
Chnl
X
P
B
M
DMA
Ca
p
1
Chnl
X
P
B
M
DMA
Ca
p
0
Chnl
X
Watchdog
Chnl
X
Buffe
rE
m
pty
Chnl
X
DMA
Comp
Chnl
X
PBM
Error
Chnl
X
P
B
M
Ac
ti
v
e
Reserved for Chnl 1/3
SA
TA
IN
T
X
P
B
M
Rd-Wr
R
eserved
PB
M
Enable
This register defines the second PCI bus master register for Channel X in the SiI3114. The system must access
these register bits through this address to enable the Large Block Transfer Mode.
The register bits are defined below.
Bit [31:24]: (R) These bits are copies of PCI Bus Master Channel X+1 bits. This bit field (and bits 15 to 5)
appears only in the Channel 0 (offset 10H) and Channel 2 (offset 210H) registers; this bit field is reserved in
the Channel 1 (offset 18H) and Channel 3 (offset 218H) registers.
Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that all channels can operate as PCI bus master at any time.
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