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參數(shù)資料
| 型號(hào)： | SII3114CTU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 91/127頁(yè) |
| 文件大小： | 564K |
| 代理商： | SII3114CTU |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
58
2007 Silicon Image, Inc.
Bit [24]: Chnl2 Int Block (R/W) – Channel 2 Interrupt Block. This bit is set to block interrupts from Channel
2.
Bit [23]: Chnl1 Int Block (R/W) – Channel 1 Interrupt Block. This bit is set to block interrupts from Channel
1.
Bit [22]: Chnl0 Int Block (R/W) – Channel 0 Interrupt Block. This bit is set to block interrupts from Channel
0.
Bit [21:17]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [16]: M66EN (R) – PCI 66MHz Enable. This bit reflects input pin M66EN.
Bit [15:12]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [11]: Chnl2 Module Rst (R/W) – Channel 2 Module Reset. This bit is set to reset the interface logic for
Channel 2.
Bit [10]: Chnl3 Module Rst (R/W) – Channel 3 Module Reset. This bit is set to reset the interface logic for
Channel 3.
Bit [09]: FF2 Module Rst (R/W) – FF2 Module Reset. This bit is set to reset the FIFO logic in Channel 2.
Bit [08]: FF3 Module Rst (R/W) – FF3 Module Reset. This bit is set to reset the FIFO logic in Channel 3.
Bit [07]: Chnl0 Module Rst (R/W) – Channel 0 Module Reset. This bit is set to reset the interface logic for
Channel 0.
Bit [06]: Chnl1 Module Rst (R/W) – Channel 1 Module Reset. This bit is set to reset the interface logic for
Channel 1.
Bit [05]: FF0 Module Rst (R/W) – FF0 Module Reset. This bit is set to reset the FIFO logic in Channel 0.
Bit [04]: FF1 Module Rst (R/W) – FF1 Module Reset. This bit is set to reset the FIFO logic in Channel 1.
Bit [03:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01]: ARB Module Rst (R/W) – ARB Module Reset. This bit is set to reset the internal logic for the
Arbiter.
Bit [00]: PBM Module Rst (R/W) – PBM Module Reset. This bit is set to reset the internal logic for the PCI
Bus Master state machine.
System Software Data Register
Address Offset: 4CH / 24CH
Access Type: Read/Write
Reset Value: Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
System Software Data
This register is used by the software for non-resettable data storage. The contents are unknown on power-up and
are never cleared by any type of reset.
Flash Memory Address – Command + Status
Address Offset: 50H
Access Type: Read/Write
Reset Value: 0x0800_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
M
e
m
Init
Done
M
e
m
Init
M
e
m
A
c
cess
St
art
M
e
m
A
ccess
Type
Reserved
Memory Address
This register defines the address and command/status register for flash memory interface in the SiI3114. The
register bits are defined below.
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