參數(shù)資料
型號(hào): SC16C2552IA44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual UART with 16-byte transmit and receive FIFOs
中文描述: 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 5/38頁
文件大?。?/td> 579K
代理商: SC16C2552IA44
Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
5 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
CTSA, CTSB
40, 28
I
Clear to Send (Active-LOW).
These inputs are associated with individual UART
channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is
ready to accept transmit data from the SC16C2552. Status can be tested by reading
MSR[4].
Data Set Ready (Active-LOW).
These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the UART.
Data Terminal Ready (Active-LOW).
These outputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates that the SC16C2552 is
powered-on and ready. This pin can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This
pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
Ring Indicator (Active-LOW).
These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem has received a ringing
signal from the telephone line. A logic 1 transition on this input pin will generate an
interrupt.
Request to Send (Active-LOW).
These outputs are associated with individual UART
channels, A through B. A logic 0 on the RTS pin indicates the receiver is ready to
receive data. Writing a logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating that the receiver is ready to receive data. After a reset this pin will be
set to a logic 1.
Receive data A, B.
These inputs are associated with individual serial channel data to
the SC16C2552 receive input circuits, A-B. The RX signal will be a logic 1 during reset,
idle (no data), or when the transmitter is disabled. During the local loop-back mode, the
RX input pin is disabled and TX data is connected to the UART RX input, internally.
Transmit data A, B.
These outputs are associated with individual serial transmit
channel data from the SC16C2552. The TX signal will be a logic 1 during reset, idle (no
data), or when the transmitter is disabled. During the local loop-back mode, the TX
output pin is disabled and TX data is internally connected to the UART RX input.
DSRA, DSRB
41, 29
I
DTRA, DTRB
37, 27
O
RIA, RIB
43, 31
I
RTSA, RTSB
36, 23
O
RXA, RXB
39, 25
I
TXA, TXB
38, 26
O
Table 2:
Symbol
Pin description
…continued
Pin
Type
Description
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