參數(shù)資料
型號： SC16C2552IA44
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Dual UART with 16-byte transmit and receive FIFOs
中文描述： 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù)： 25/38頁
文件大?。?/td> 579K
代理商： SC16C2552IA44
Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
25 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
10. Dynamic characteristics
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
= 333 ns (for Baudrate
max
= 1.5 Mbits/s)
= 1
μ
s (for Baudrate
max
= 460.8 kbits/s)
= 4
μ
s (for Baudrate
max
= 115.2 kbits/s)
When in
both
DMA mode 0
and
FIFO enable mode, the write cycle delay should be larger than one x
1
, clock cycle.
[3]
Table 25:
T
amb
=
40
°
C to +85
°
C; V
CC
= 2.5 V 3.3 V or 5.0 V
±
10%, unless otherwise specified.
Symbol
Parameter
AC electrical characteristics
Conditions
2.5 V
Max
-
48
-
-
-
-
-
-
77
15
-
-
[2]
-
-
-
-
100
100
3.3 V
Max
-
80
-
-
-
-
-
-
26
15
-
-
[2]
-
-
-
-
33
24
5.0 V
Max
-
80
-
-
-
-
-
-
23
15
-
-
[2]
-
-
-
-
29
23
Unit
Min
10
-
0
0
10
77
0
20
-
-
10
20
0
25
20
15
-
-
Min
6
-
0
0
10
26
0
20
-
-
10
20
0
25
20
5
-
-
Min
6
t
1w
, t
2w
t
3w
t
6s
t
6h
t
7d
t
7w
t
7h
t
9d
t
12d
t
12h
t
13d
t
13w
t
13h
t
15d
t
16s
t
16h
t
17d
t
18d
clock pulse duration
oscillator/clock frequency
address set-up time
address hold time
IOR delay from chip select
IOR strobe width
chip select hold time from IOR
read cycle delay
delay from IOR to data
data disable time
IOW delay from chip select
IOW strobe width
chip select hold time from IOW
write cycle delay
data set-up time
data hold time
delay from IOW to output
delay to set interrupt from Modem
input
delay to reset interrupt from IOR
delay from stop to set interrupt
delay from IOR to reset interrupt
delay from start to set interrupt
delay from IOW to transmit start
delay from IOW to reset interrupt
delay from stop to set RXRDY
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
delay from start to reset TXRDY
Reset pulse width
baud rate divisor
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1]
0
0
10
23
0
20
-
-
10
15
0
20
15
5
-
-
25 pF load
25 pF load
25 pF load
25 pF load
[3]
25 pF load
25 pF load
t
19d
t
20d
t
21d
t
22d
t
23d
t
24d
t
25d
t
26d
t
27d
t
28d
t
RESET
N
25 pF load
-
-
-
-
8
-
-
-
-
-
200
1
100
1
100
100
24
100
1
100
100
8
-
2
16
1
-
-
-
-
8
-
-
-
-
-
40
1
24
1
29
45
24
45
1
45
45
8
-
2
16
1
-
-
-
-
8
-
-
-
-
-
40
1
23
1
28
40
24
40
1
40
40
8
-
2
16
1
ns
R
clk
ns
ns
R
clk
ns
R
clk
ns
ns
R
clk
ns
R
clk
25 pF load
IOWstrobe
max
max
)
--------------------------------------
=
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