參數(shù)資料
型號(hào)： SC16C2552IA44
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Dual UART with 16-byte transmit and receive FIFOs
中文描述： 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁(yè)數(shù)： 17/38頁(yè)
文件大?。?/td> 579K
代理商： SC16C2552IA44
Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
17 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Interrupt Status Register (ISR)
The SC16C2552 provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.
Table 10 “Interrupt source”
shows the data values
(bits 0-3) for the four prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 10:
Priority
level
1
2
2
3
4
Interrupt source
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
Table 11:
Bit
7-6
Interrupt Status Register bits description
Symbol
Description
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2552 mode.
Logic 0 or cleared = default condition.
ISR[5-4]
Not used; initialized to a logic 0.
Logic 0 or cleared = default condition.
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
Table 10
).
Logic 0 or cleared = default condition.
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
5-4
3-1
0
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