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| 型號(hào)： | SC16C2552IA44 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual UART with 16-byte transmit and receive FIFOs |
| 中文描述： | 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 15/38頁 |
| 文件大?。?/td> | 579K |
| 代理商： | SC16C2552IA44 |
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Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
15 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = 0):
Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) at the MF pin will go to a logic 0 whenever
the Receive Holding Register (RHR) is loaded with a character and the MF register is
set to the RXRDY mode.
Mode 1 (FCR bit 3 = 1):
Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when the transmit FIFO has at least one empty location.
TXRDY remains a logic 0 as long as one empty FIFO location is available. The
receive interrupt is set when the receive FIFO fills to the programmed trigger level.
However, the FIFO continues to fill regardless of the programmed level until the FIFO
is full. RXRDY at the MF pin remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level, and the MF register is set to the RXRDY mode.
7.3.2
FIFO mode
Table 8:
Bit
7-6
FIFO Control Register bits description
Symbol
Description
FCR[7]
(MSB),
FCR[6]
(LSB)
FIFO equals the programmed trigger level. However, the FIFO will
continue to be loaded until it is full. Refer to
Table 9
.
FCR[5-4]
Not used; initialized to logic 0.
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C2552 is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO
mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and
when there are no characters in the transmit FIFO or transmit
holding register, the TXRDY pin will be a logic 0. Once active, the
TXRDY pin will go to a logic 1 after the first character is loaded into
the transmit holding register.
Receive operation in mode ‘0’:
When the SC16C2552 is in
16C450 mode, or in the FIFO mode (FCR[0] = logic 1;
FCR[3] = logic 0) and there is at least one character in the receive
FIFO, the RXRDY signal at the MF pin will be a logic 0. Once
active, the RXRDY signal at the MF pin will go to a logic 1 when
there are no more characters in the receiver. NOTE: The AFR
register must be set to the RXRDY mode prior to any possible
reading of the RXRDY signal.
RCVR trigger. These bits are used to set the trigger level for the
receive FIFO interrupt.
An interrupt is generated when the number of characters in the
5-4
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SC16C2552IA44,512 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552IA44,518 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552IA44,529 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C550B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs |
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