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| 型號： | SC16C2552IA44 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual UART with 16-byte transmit and receive FIFOs |
| 中文描述： | 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 14/38頁 |
| 文件大小： | 579K |
| 代理商： | SC16C2552IA44 |
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Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
14 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.2.1
IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit
and the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred
from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is
empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated
when the transmit FIFO is empty due to the unloading of the data by the TSR and
UART for transmission via the transmission media. The interrupt is cleared either
by reading the ISR register, or by loading the THR with new data characters.
7.2.2
IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2552 in the FIFO
polled mode of operation. In this mode, interrupts are not generated and the user
must poll the LSR register for TX and/or RX data status. Since the receiver and
transmitter have separate bits in the LSR either or both can be used in the polled
mode by selecting respective transmit or receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will show if any FIFO data errors occurred.
0
IER[0]
Receive Holding Register. In the 16C450 mode, this interrupt will
be issued when the RHR has data, or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued when the
FIFO has reached the programmed trigger level or is cleared when
the FIFO drops below the trigger level.
Logic 0 = Disable the receiver ready (ISR level 2, RXRDY)
interrupt (normal default condition).
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
Table 7:
Bit
Interrupt Enable Register bits description
…continued
Symbol
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C2552IA44,512 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552IA44,518 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552IA44,529 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C550B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs |
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