參數(shù)資料
型號: SC16C2552IA44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual UART with 16-byte transmit and receive FIFOs
中文描述: 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 3/38頁
文件大小: 579K
代理商: SC16C2552IA44
Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
3 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5.
Pinning information
5.1 Pinning
5.2 Pin description
Fig 2.
PLCC44 pin configuration.
SC16C2552IA44
002aaa124
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
1
1
2
2
2
2
2
2
2
2
2
6
5
4
3
2
1
4
4
4
4
4
D
D
D
D
D
T
V
C
R
C
D
C
C
M
I
R
G
R
I
R
T
D
C
D5
D6
D7
A0
XTAL1
GND
XTAL2
A1
A2
CHSEL
INTB
RXA
TXA
DTRA
RTSA
MFA
INTA
Vcc
TXRDYB
RIB
CDB
DSRB
Table 2:
Symbol
A2-A0
Pin description
Pin
10, 14,
15
16
Type
I
Description
Register select.
A0-A2 are used during read and write operations to select the UART
register to read from or write to.
Channel Select.
UART channel A or B is selected by the logical state of this pin when
the CS is a logic 0. A logic 0 on CHSEL selects the UART channel ‘B’, while a logic 1
selects UART channel ‘A’.
Chip Select (Active-LOW).
This function is selects channel ‘A’ or ‘B’, in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between the
user CPU and the SC16C2552, or the SC16C2552 and the CPU for a channel selected
by CHSEL. MF[0] overrides CHSEL while in the write cycle mode, allowing the user to
write both channel registers simultaneously with one write cycle.
Data bus (bi-directional).
These pins are the 8-bit, 3-State data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
Signal and power ground.
CHSEL
I
CS
18
I
D0-D7
2-9
I/O
GND
12, 22
I
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