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參數(shù)資料
| 型號： | SC16C2552IA44 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual UART with 16-byte transmit and receive FIFOs |
| 中文描述： | 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 16/38頁 |
| 文件大?。?/td> | 579K |
| 代理商： | SC16C2552IA44 |
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Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
16 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
3
(continued)
Transmit operation in mode ‘1’:
When the SC16C2552 is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin
will be a logic 1 when the transmit FIFO is completely full. It will be
a logic 0 if one or more FIFO locations are empty.
Receive operation in mode ‘1’:
When the SC16C2552 is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has
been reached, or a Receive Time-Out has occurred, the RXRDY
signal at the MF pin will go to a logic 0. Once activated, it will go to
a logic 1 after there are no more characters in the FIFO.
NOTE: The AFR register must be set to the RXRDY mode prior to
any possible reading of the RXRDY signal.
XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets
the FIFO counter logic (the transmit shift register is not cleared
or altered). This bit will return to a logic 0 after clearing the FIFO.
RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
FIFOs enabled.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
2
FCR[2]
1
FCR[1]
0
FCR[0]
Table 9:
FCR[7]
0
0
1
1
RCVR trigger levels
FCR[6]
0
1
0
1
RX FIFO trigger level
01
04
08
14
Table 8:
Bit
FIFO Control Register bits description
…continued
Symbol
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C2552IA44,512 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552IA44,518 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552IA44,529 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C550B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs |
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