參數(shù)資料
型號(hào)： SC16C2552IA44
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Dual UART with 16-byte transmit and receive FIFOs
中文描述： 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁(yè)數(shù)： 12/38頁(yè)
文件大?。?/td> 579K
代理商： SC16C2552IA44
Philips Semiconductors
SC16C2552
Dual UART with 16-byte transmit and receive FIFOs
Product data
Rev. 03 — 20 June 2003
12 of 38
9397 750 11636
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Register descriptions
Table 6
details the assigned bit functions for the SC16C2552 internal registers. The
assigned bit functions are further defined in
Section 7.1
through
Section 7.11
.
[1]
[2]
The value shown in represents the register’s initialized HEX value; X = n/a.
The General Register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 0. Set A is accessible when CHSEL is a
logic 1, and set is accessible when CHSEL is a logic 0.
The Baud Rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 1 for the register set (A/B)
being accessed.
[3]
Table 6:
A2
General Register Set
[2]
0
0
0
0
0
0
0
0
1
SC16C2552 internal registers
A0
Register
A1
Default
[1]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RHR
THR
IER
XX
XX
00
bit 7
bit 7
0
bit 6
bit 6
0
bit 5
bit 5
0
bit 4
bit 4
0
bit 3
bit 3
modem
status
interrupt
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits
bit 1
bit 1
transmit
holding
register
interrupt
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
bit 0
bit 0
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
RCVR
trigger
(LSB)
FIFOs
enabled
0
0
DMA
mode
select
INT
priority
bit 2
parity
enable
FIFO
enable
0
1
0
ISR
01
0
0
INT
status
0
1
1
LCR
00
divisor
latch
enable
0
set
break
set parity even
parity
word
length
bit 0
DTR
1
0
0
MCR
00
0
0
loop
back
OP A/B,
INTA/B
enable
framing
error
OP1
1
0
1
LSR
60
FIFO
data
error
CD
bit 7
THRand
TSR
empty
RI
bit 6
THR
empty
break
interrupt
parity
error
overrun
error
receive
data
ready
CTS
bit 0
1
1
Special Register Set
[3]
0
0
0
0
0
1
0
1
0
1
1
0
1
MSR
SPR
X0
FF
DSR
bit 5
CTS
bit 4
CD
bit 3
RI
bit 2
DSR
bit 1
DLL
DLM
AFR
XX
XX
00
bit 7
bit 15
bit 7
bit 6
bit 14
bit 6
bit 5
bit 13
bit 5
bit 4
bit 12
bit 4
bit 3
bit 11
bit 3
bit 2
bit 10
bit 2
bit 1
bit 9
bit 1
bit 0
bit 8
bit 0
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