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參數(shù)資料
| 型號： | SAB-XC167CI-16F20F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 0.50 MM PITCH, PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 68/80頁 |
| 文件大?。?/td> | 2477K |
| 代理商： | SAB-XC167CI-16F20F |
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XC167
Derivatives
Timing Parameters
Data Sheet
66
V1.1, 2003-06
Preliminary
Variable Memory Cycles
External bus cycles of the XC167 are executed in five subsequent cycle phases (AB, C,
D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Table 18
Programmable Bus Cycle Phases (see timing diagrams)
Bus Cycle Phase
Parameter
Valid Values Unit
Address setup phase, the standard duration of this
phase (1
…2 TCP) can be extended by 0 …3 TCP if
the address window is changed
tpAB
1
…2 (5)
TCP
Command delay phase
tpC
0
…3
TCP
Write Data setup / MUX Tristate phase
tpD
0
…1
TCP
Access phase
tpE
1
…32
TCP
Address / Write Data hold phase
tpF
0
…3
TCP
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